FM3316 datasheet(4/28 Pages) RAMTRON

4 / 28 page

FM33256/FM3316 SPI Companion w/ FRAM

Rev. 2.0

Feb. 2009

Page 4 of 28

Overview

The FM33xx devices combine a serial nonvolatile

RAM with a real-time clock (RTC) and a processor

companion. The companion is a highly integrated

peripheral including a processor supervisor, analog

comparator, a nonvolatile counter, and a serial

number.

The

FM33xx

integrates

these

complementary

but

distinct

functions

under

common interface in a single package. Although

monolithic, the product is organized as two logical

devices. The first is a memory and the second is the

companion

which

includes

all

the

remaining

functions. From the system perspective they appear

to be two separate devices with unique op-codes on

the serial bus.

The memory is organized as a standalone nonvolatile

SPI memory using standard op-codes. The real-time

clock and supervisor functions are accessed under

their own op-codes. The clock and supervisor

functions are controlled by 30 special function

registers. The RTC/alarm and some control registers

are maintained by the power source on the VBAK

pin, allowing them to operate from battery or backup

capacitor power when VDD drops below a set

threshold. Each functional block is described below.

Memory Operation

The FM33xx products are available in memory sizes

of 16Kb and 256Kb. The two devices are software

compatible; that is, both versions use consistent two-

byte addressing for the memory device. This makes

both devices the same as its standalone memory

counterparts, such as the FM25L16.

Memory is organized in bytes, for example the

256Kb memory is 32,768 x 8. The memory is based

on F-RAM technology. Therefore it can be treated as

RAM and is read or written at the speed of the SPI

bus with no delays for write operations. It also offers

effectively unlimited write endurance unlike other

nonvolatile memory technologies. The SPI protocol

is described on page 18.

The memory array can be write-protected by

software. Two bits in the Status Register control the

protection setting. Based on the setting, the protected

addresses cannot be written. The Status Register &

Write Protection is described in more detail on page

20.

Processor Companion

In addition to nonvolatile RAM, the FM33xx devices

incorporate a real-time clock with alarm and highly

integrated processor companion. The companion

includes a low-VDD reset, a programmable watchdog

timer,

16-bit

nonvolatile

event

counter,

comparator for early power-fail detection or other

purposes, and a 64-bit serial number.

Processor Supervisor

Supervisors provide a host processor two basic

functions: Detection of power supply fault conditions

and a watchdog timer to escape a software lockup

condition. Both FM33xx devices have a reset pin

(/RST) to drive a processor reset input during power

faults, power-up, and software lockups. It is an open

drain output with a weak internal pull-up to VDD.

This allows other reset sources to be wire-OR’d to

the /RST pin. When VDD is above the programmed

trip point, /RST output is pulled weakly to VDD. If

VDD drops below the reset trip point voltage level

(VTP), the /RST pin will be driven low. It will remain

low until VDD falls too low for circuit operation

which is the VRST level. When VDD rises again above

VTP, /RST continues to drive low for at least 50 ms

(tRPU) to ensure a robust system reset at a reliable VDD

level. After tRPU has been met, the /RST pin will

return to the weak high state. While /RST is asserted,

serial bus activity is locked out even if a transaction

occurred as VDD dropped below VTP. A memory

operation started while VDD is above VTP will be

completed internally.

Table 1 below shows how bits VTP(1:0) control the

trip point of the low-VDD reset. They are located in

low when VDD is below the selected VTP voltage, and

the SPI interface and F-RAM array will be locked

out. Figure 2 illustrates the reset operation in

response to a low VDD.

Table 1.

VTP Setting

VTP1

VTP0

2.6V

2.75V

2.9V

3.0V

VDD

VTP

tRPU

RST

Figure 2. Low VDD Reset

A watchdog timer can also be used to drive an active

reset

signal.

The

watchdog

free-running

programmable timer. The timeout period can be

software programmed from 60 ms to 1.8 seconds in

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