FM3316 datasheet(18/28 Pages) RAMTRON

18 / 28 page

FM33256/FM3316 SPI Companion w/ FRAM

Rev. 2.0

Feb. 2009

Page 18 of 28

Serial Peripheral Interface – SPI Bus

The FM33xx employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to

16 MHz. This high-speed serial bus provides high

performance

serial

communication

host

microcontroller.

Many common

microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM33xx devices operate in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. A typical system

configuration uses an FM33xx and a standalone SPI

device with a microcontroller that has a dedicated

SPI port, as Figure 10 illustrates. Note that the clock,

data-in, and data-out pins are common among all

devices. The /CS pins must be driven separately for

the FM33xx and each additional SPI device.

Figure 10. System Configuration with SPI port

For a microcontroller that has no dedicated SPI bus, a

general purpose port may be used. To reduce

hardware resources on the controller, it is possible to

connect the two data pins together. Figure 11 shows a

configuration that uses only three pins.

Microcontroller

FM33xx

SI SCK

Figure 11. System Configuration without SPI port

Protocol Overview

The SPI interface is a synchronous serial interface

using clock and data pins. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM33xx will begin monitoring

the clock and data lines. The relationship between

the falling edge of /CS, the clock and data is dictated

by the SPI mode. The device will make a

determination of the SPI mode on the falling edge of

each chip select. While there are four such modes,

the FM33xx supports only modes 0 and 3. Figure 12

shows the required signal relationships for modes 0

and 3.

For both modes, data is clocked into the

FM33xx on the rising edge of SCK and data is

expected on the first rising edge after /CS goes

active. If the clock starts from a high state, it will

fall prior to the first data transfer in order to create

the first rising edge.

SPI Mode 0: CPOL=0, CPHA=0

SPI Mode 3: CPOL=1, CPHA=1

Figure 12. SPI Modes 0 & 3

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the device. After

/CS is activated the first byte transferred from the

bus master is the op-code. Following the op-code,

any addresses and data are then transferred. Note

that the WREN and WRDI op-codes are commands

with no subsequent data transfer.

Important: The /CS pin must go inactive after an

operation is complete and before a new op-code

can be issued. There is only one valid op-code per

active chip select.

Data Transfer

All data transfers to and from the FM33xx occur in

8-bit groups. They are synchronized to the clock

signal (SCK), and they transfer most significant bit

(MSB) first.

Serial inputs are registered on the

rising edge of SCK. Outputs are driven from the

falling edge of SCK.

FM3316 Datasheet(PDF) 18 Page - Ramtron International Corporation

FM3316 Datasheet(HTML) 18 Page - Ramtron International Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL