Rev. 1.00

15

November 22, 2011

HT16C21

different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are

Data Validity

The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the

data line can only change when the clock signal on the SCL line is Low as shown in the diagram.

SDA

SCL

Data line stable;

Data valid

Change of data

allowed

START and STOP Conditions

● A high to low transition on the SDA line while SCL is high defines a START condition.

● A low to high transition on the SDA line while SCL is high defines a STOP condition.

after the START condition. The I2C interface is considered to be free again a certain time after the STOP

condition.

respects, the START(S) and repeated START (Sr) conditions are functionally identical.

P

S

SDA

SCL

SDA

SCL

START condition

STOP condition

Byte Format

Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,

MSB, first.

S

or

Sr

P

or

Sr

SDA

SCL

1

2

7

8

9

ACK

1

2

3-8

9

ACK

P

Sr