AM1806 datasheet(37/244 Pages) TI1

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AM1806

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SPRS658C

– FEBRUARY 2010 – REVISED APRIL 2011

2.7.15 Multichannel Audio Serial Ports (McASP)

Table 2-17. Multichannel Audio Serial Ports Terminal Functions

SIGNAL

POWER

TYPE(1)

PULL(2)

DESCRIPTION

GROUP(3)

NAME

NO.

McASP0

AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]

I/O

CP[1]

AXR14 / CLKR1 / GP0[6]

I/O

CP[2]

AXR13 / CLKX1 / GP0[5]

I/O

CP[2]

AXR12 / FSR1 / GP0[4]

I/O

CP[2]

AXR11 / FSX1 / GP0[3]

I/O

CP[2]

AXR10 / DR1 / GP0[2]

I/O

CP[2]

AXR9 / DX1 / GP0[1]

I/O

CP[2]

AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]

I/O

CP[3]

McASP0 serial data

AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /

I/O

CP[4]

PRU0_R31[7]

AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]

I/O

CP[5]

AXR5 / CLKX0 / GP1[13]

I/O

CP[5]

AXR4 / FSR0 / GP1[12]

I/O

CP[5]

AXR3 / FSX0 / GP1[11]

I/O

CP[5]

AXR2 / DR0 / GP1[10]

I/O

CP[5]

AXR1 / DX0 / GP1[9]

I/O

CP[5]

AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0

I/O

CP[6]

AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /

I/O

CP[0]

McASP0 transmit master clock

PRU0_R31[17]

ACLKX / PRU0_R30[19]/ GP0[14]/ PRU0_R31[21]

I/O

CP[0]

McASP0 transmit bit clock

AFSX / GP0[12] / PRU0_R31[19]

I/O

CP[0]

McASP0 transmit frame sync

AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /

I/O

CP[0]

McASP0 receive master clock

PRU0_R31[18]

ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]

I/O

CP[0]

McASP0 receive bit clock

AFSR / GP0[13] / PRU0_R31[20]

I/O

CP[0]

McASP0 receive frame sync

AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /

I/O

CP[0]

McASP0 mute output

PRU0_R31[16]

(1)

I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2)

IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the

device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,

an external pull-up can be used. For electrical specifications on the pull-up and and internal pull-down circuits, see the Device Operating

Conditions section.

(3)

This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

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