9FG430 datasheet(14/18 Pages) IDT

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IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI

1681C—08/26/10

9FG430

Four Output Differential Frequency Generator for PCIe Gen3 and QPI

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Pin #

Name

Control Function

Type

Default

Bit 7

M/N_Enable

M/N Prog. Enable

Disable

Enable

Bit 6

Bit 5

REFOUT_En

REFOUT Enable

Disable

Enable

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: PLL Frequency Control Register

Pin #

Name

Control Function

Type

Default

Bit 7

PLL N Div8

N Divider Prog bit 8

Bit 6

PLL N Div9

N Divider Prog bit 9

Bit 5

PLL M Div5

Bit 4

PLL M Div4

Bit 3

PLL M Div3

Bit 2

PLL M Div2

Bit 1

PLL M Div1

Bit 0

PLL M Div0

Byte 10

The decimal representation of M

and N Divider in Byte 10 and 11 will

configure the PLL VCO frequency.

Default at power up = latch-in or

Byte 0 Rom table. VCO Frequency

= fXTAL x [NDiv(9:0)+8] /

[MDiv(5:0)+2]. The user does NOT

need to program these resgisters

for standard frequencies.

M Divider Programming

bit (5:0)

Reserved

Byte 9

Reserved

Byte 8

Byte 7

Reserved

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