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ACS42200 Datasheet(PDF) 39 Page - Integrated Device Technology |
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ACS42200 Datasheet(HTML) 39 Page - Integrated Device Technology |
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39 / 89 page ![]() 39 V1.2 1/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422X00 ACS422x00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • PWM Control 1 Register • PWM Control 2 Register • PWM Control 3 Register 3.15. Other Output Capabilities Each audio analog output can be separately enabled. Disabling outputs serves to reduce power consumption, and is the default state of the device. Register Address Bit Label Type Default Description R67 (43h) PWM1 7 RSVD R 0 Reserved 6:2 dithpos[4:0] RW 0 Dither position, where dither inserted after NS. 0,1,2 = dither bits 2:0 4 = dither bits 3:1 5 = dither bits 4:1 .... 19 = dither bits 19:17 1 dith_range RW 0 1 = dither -1 to +1, 0 = -3 to +3 0 dithclr RW 0 1 = disable dither Table 44. PWM1 Register Register Address Bit Label Type Default Description R68 (44h) PWM2 7:2 dvalue[5:0] RW 18h dvalue constant field 1 pwm_outflip RW 0 1 = swap pwm a/b output pair for all channels The control lines to the power stage are swapped inverting the output signal. 0 pwm_outmode RW 1 1 = tristate, 0 = binary Table 45. PWM2 Register Register Address Bit Label Type Default Description R69 (45h) PWM3 7:6 outctrl[1:0] RW 00 pwm output muxing 0 = normal 1 = swap 0/1 2 = ch0 on both 3 = ch1 on both 5:0 cvalue[5:0] RW 0Ah tristate constant field, must be even and not 0 Table 46. PWM3 Register |
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