ICS87972I datasheet(11/17 Pages) IDT

11 / 17 page

87972DYI

www.idt.com

REV. E JUNE 25, 2010

ICS87972I

LOW SKEW, 1-TO-12

LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS87972I provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD, VDDA and VDDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 3 illustrates how

a 10

Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V

DDA pin.

FIGURE 3. POWER SUPPLY FILTERING

DDA

μF

.01

μF

3.3V

.01

μF

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

resistor can be tied from XTAL_IN to ground.

CLK INPUT:

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the CLK input to

ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. We

recommend that there is no trace attached.

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