ICS87972I datasheet(12/17 Pages) IDT

12 / 17 page

87972DYI

www.idt.com

REV. E JUNE 25, 2010

ICS87972I

LOW SKEW, 1-TO-12

LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

APPLICATION SCHEMATIC EXAMPLE

Figure 4 shows an application schematic example of

ICS87972I. This example provides general handling of input/

output termination, logic control input and power supply filter-

ing. In this example, the clock inputs are driven by LVCMOS

drivers. Series termination for LVCMOS drivers is shown. Ad-

ditional LVCMOS termination approaches are shown in the

LVCMOS Termination Application Note. The logic control in-

R11

Zo = 50

R10

RD2

(U1-17)

(U1-33)

VDD

VDD=3.3V

RD1

Not Install

RU1

0.1uF

(U1-37)

Zo = 50

Logic Input Pin Examples

87972i

GNDI

nMR/OE

FRZ_CLK

FRZ_DATA

FSEL_FB2

PLL_SEL

REF_SEL

CLK_SEL

CLK0

CLK1

XTAL1

XTAL2

VDDA

GNDO

QB0

VDDO

QB1

GNDO

QB2

VDDO

QB3

EXT_FB

GNDO

QFB

VDD

FSEL_FB0

Zo = 50

0.1uF

Ro=16 Ohm

LVCMOS

(U1-45)

VDD

Zo = 50

To Logic

Input

pins

R12

LVCMOS

Ro=16 Ohm

LVCMOS

Set Logic

Input to

'0'

VDD

C11

0.01u

VDDO=3.3V

LVCMOS

Zo = 50

R13

0.1uF

R14

10 - 15

Zo = 50

VDD

0.1uF

(U1-49)

0.1uF

To Logic

Input

pins

Ro=16 Ohm

LVCMOS

RU2

Not Install

VDDO

Ro=16 Ohm

LVCMOS

VDDO

(U1-22)

VDD

Zo = 50

VDD

Set Logic

Input to

'1'

C16

10u

0.1uF

put can be either hardwired on the board or controlled by

LVCMOS drivers. In this example, both hardwired and

LVCMOS driver controlling the logic input are shown. For the

power supply pins, it is recommended at least one decoupling

capacitor per power pin. The decoupling capacitors should

be placed as close to the power pins as possible.

FIGURE 4. ICS87972I LAYOUT SCHEMATIC

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