HT67F60 datasheet(134/242 Pages) HOLTEK

134 / 242 page

Rev. 1.50

134

March 06 , 2012

Rev. 1.50

135

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

Capture Input Mode

00: Input capture at rising edge of TP1A

01: Input capture at falling edge of TP1A

10: Input capture at falling/rising edge of TP1A

11: Input capture disabled

Timer/counter Mode

Unused

These two bits are used to determine how the TM output pin changes state when a

certain condition is reached. The function that these bits select depends upon in which

mode the TM is running.

In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the

TM output pin changes state when a compare match occurs from the Comparator A.

The TM output pin can be setup to switch high, switch low or to toggle its present

state when a compare match occurs from the Comparator A. When the bits are both

zero, then no change will take place on the output. The initial value of the TM output

pin should be setup using the T1AOC bit in the TM1C1 register. Note that the output

level requested by the T1AIO1 and T1AIO0 bits must be different from the initial

value setup using the T1AOC bit otherwise no change will occur on the TM output pin

when a compare match occurs. After the TM output pin changes state it can be reset to

its initial level by changing the level of the T1ON bit from low to high.

In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin

changes state when a certain compare match condition occurs. The PWM output

function is modified by changing these two bits. It is necessary to change the values of

the T1AIO1 and T1AIO0 bits only after the TM has been switched off. Unpredictable

PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is

running.

Bit 3

T1AOC: TP1A Output control bit

Compare Match Output Mode

0: Initial low

1: Initial high

PWM Mode/ Single Pulse Output Mode

0: Active low

1: Active high

This is the output control bit for the TM output pin. Its operation depends upon

whether TM is being used in the Compare Match Output Mode or in the PWM Mode/

Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In

the Compare Match Output Mode it determines the logic level of the TM output pin

before a compare match occurs. In the PWM Mode it determines if the PWM signal is

active high or active low.

Bit 2

T1APOL: TP1A Output polarity Control

0: Non-invert

1: Invert

This bit controls the polarity of the TP1A output pin. When the bit is set high the TM

output pin will be inverted and not inverted when the bit is zero. It has no effect if the

TM is in the Timer/Counter Mode.

Bit 1

T1CDN: TM1 Counter count up or down flag

0: Count up

1: Count down

Bit 0

T1CCLR: Select TM1 Counter clear condition

0: TM1 Comparator P match

1: TM1 Comparator A match

This bit is used to select the method which clears the counter. Remember that the

Enhanced TM contains three comparators, Comparator A, Comparator B and

Comparator P, but only Comparator A or Comparator P can be selected to clear the

internal counter. With the T1CCLR bit set high, the counter will be cleared when a

HT67F60 Datasheet(PDF) 134 Page - Holtek Semiconductor Inc

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