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AFS090 Datasheet(PDF) 275 Page - Microsemi Corporation

Part # AFS090
Description  Fusion Family of Mixed Signal FPGAs
PDF  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

AFS090 Datasheet(HTML) 275 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
3 - 25
PS-CELL = NS-CELL * (PAC5 + (α1 / 2) * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PS-CELL = 0 W
Combinatorial Cells Dynamic Contribution—PC-CELL
Operating Mode
PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PC-CELL = 0 W
Routing Net Dynamic Contribution—PNET
Operating Mode
PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PNET = 0 W
I/O Input Buffer Dynamic Contribution—PINPUTS
Operating Mode
PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PINPUTS = 0 W
I/O Output Buffer Dynamic Contribution—POUTPUTS
Operating Mode
POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 3-17 on page 3-27.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
POUTPUTS = 0 W



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