AFS090 datasheet(279/334 Pages) MICROSEMI

279 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

3 - 29

PS-CELL = 0 W

PC-CELL = 0 W

PNET = 0 W

PLOGIC = 0 W

I/O Input and Output Buffer Contribution—PI/O

This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high

output slew and driving a 35 pF output load.

FCLK = 50 MHz

Number of input pins used: NINPUTS = 30

Number of output pins used: NOUTPUTS = 40

Estimated I/O buffer toggle rate:

2 = 0.1 (10%)

Estimated IO buffer enable rate:

1 = 1 (100%)

Operating Mode

PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK

PINPUTS = 30 * (0.1 / 2) * 0.01739 * 50

PINPUTS = 1.30 mW

POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK

POUTPUTS = 40 * (0.1 / 2) * 1 * 0.4747 * 50

POUTPUTS = 47.47 mW

PI/O = PINPUTS + POUTPUTS

PI/O = 1.30 mW + 47.47 mW

PI/O = 48.77 mW

Standby Mode and Sleep Mode

PINPUTS = 0 W

POUTPUTS = 0 W

PI/O = 0 W

RAM Contribution—PMEMORY

Frequency of Read Clock: FREAD-CLOCK = 10 MHz

Frequency of Write Clock: FWRITE-CLOCK = 10 MHz

Number of RAM blocks: NBLOCKS = 20

Estimated RAM Read Enable Rate:

2 = 0.125 (12.5%)

Estimated RAM Write Enable Rate:

3 = 0.125 (12.5%)

Operating Mode

PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK)

PMEMORY = (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)

PMEMORY = 1.38 mW

Standby Mode and Sleep Mode

PMEMORY = 0 W

AFS090 Datasheet(PDF) 279 Page - Microsemi Corporation

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