AFS090 datasheet(277/334 Pages) MICROSEMI

277 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

3 - 27

RC Oscillator Dynamic Contribution—PRC-OSC

Operating Mode

PRC-OSC = PAC19

Standby Mode and Sleep Mode

PRC-OSC = 0 W

Analog System Dynamic Contribution—PAB

Operating Mode

PAB = PAC20

Standby Mode and Sleep Mode

PAB = 0 W

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 3-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Guideline

Toggle rate of VersaTile outputs

10%

I/O buffer toggle rate

10%

Table 3-17 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

Guideline

I/O output buffer enable rate

100%

RAM enable rate for read operations

12.5%

RAM enable rate for write operations

12.5%

NVM enable rate for read operations

AFS090 Datasheet(PDF) 277 Page - Microsemi Corporation

AFS090 Datasheet(HTML) 277 Page - Microsemi Corporation

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