AFS090 datasheet(318/334 Pages) MICROSEMI

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Datasheet Information

5- 2

R e v ision 2

Revision 2

(continued)

The following figures were deleted (SAR 29991). Reference was made to a new

application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs,

which covers these cases in detail (SAR 34862).

Figure 2-55 • Write Access after Write onto Same Address

Figure 2-56 • Read Access after Write onto Same Address

Figure 2-57 • Write Access after Read onto Same Address

The port names in the SRAM "Timing Waveforms", "Timing Characteristics", SRAM

tables, Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18., and

the FIFO "Timing Characteristics" tables were revised to ensure consistency with the

software names (SAR 35753).

2-66,

2-69,

2-68, 2-77

In several places throughout the datasheet, GNDREF was corrected to

ADCGNDREF (SAR 20783):

Figure 2-62 • Analog Block Macro

Table 2-36 • Analog Block Pin Description

"ADC Operation" section

2-79

2-80

2-106

The following note was added below Figure 2-76 • Timing Diagram for the

Temperature Monitor Strobe Signal:

When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad

drive strength ceases and becomes a 1 µA sink into the Fusion device. (SAR

24796).

2-95

The "Analog-to-Digital Converter Block" section was extensively revised,

reorganizing the information and adding the "ADC Theory of Operation" section and

"Acquisition Time or Sample Time Control" section. The "ADC Example" section was

reworked and corrected (SAR 20577).

2-98

Table 2-49 • Analog Channel Specifications was modified to include calibrated and

uncalibrated values for offset (AFS090 and AFS250) for the external and internal

temperature monitors. The "Offset" section was revised accordingly and now

references Table 2-49 • Analog Channel Specifications (SARs 22647, 27015).

2-97,

2-119

The "Intra-Conversion" section and "Injected Conversion" section had definitions

incorrectly interchanged and have been corrected. Figure 2-90 • Intra-Conversion

Timing Diagram and Figure 2-91 • Injected Conversion Timing Diagram were also

incorrectly interchanged and have been replaced correctly. Reference in the figure

notes to EQ 10 has been corrected to EQ 23 (SAR 20547).

2-111,

2-114,

2-115

The "Examples" section for calibrating accuracy for ADC channels were revised and

corrected to make them consistent with terminology in the associated tables (SARs

36791, 36773).

2-126

A note was added to Table 2-56 • Analog Quad ACM Byte Assignment and the

introductory text for Table 2-66 • Internal Temperature Monitor Control Truth Table,

stating that for the internal temperature monitor to function, Bit 0 of Byte 2 for all 10

Quads must be set (SAR 34418).

2-131,

2-133

tDOUT was corrected to tDIN in Figure 2-114 • Input Buffer Timing Model and Delays

(example) (SAR 37115).

2-163

The formulas in the table notes for Table 2-97 • I/O Weak Pull-Up/Pull-Down

Resistances were corrected (SAR 34751).

2-173

The AC Loading figures in the "Single-Ended I/O Characteristics" section were

updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O

Software Settings" section (SAR 34877).

2-177

Revision

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