DS1886 datasheet(21/92 Pages) MAXIM

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�� Maxim Integrated Products 21

DS1886

SFP and PON ONU Controller

with Digital LDD Interface

Figure 2. ADC Round-Robin Timing

RIGHT-SHIFT2 is determined by KRMD[1:0],

TXCTRL3[2:1] as follows:

Right-Shifting ADC Result

The right-shift operation on the ADC result is carried out

based on the contents of right-shift control registers (A2h

Table 02h, Register 8Eh and A2h Table 02h, Register

8Fh) in EEPROM. TXB, TXP, RSSIC, and RSSIF have 3

bits allocated to set the number of right-shifts. The user

must calibrate the corresponding monitors to achieve the

correct LSB weighting. Up to seven right-shift operations

are allowed and are executed as a part of every conver-

sion before the results are compared to the high and low

alarm levels, or loaded into their corresponding measure-

ment registers (Lower Memory, Registers 64h–69h). This

is true during the setup of internal calibration as well as

during subsequent data conversions.

In burst mode, right-shifting for TXP is determined by

KIMD and KRMD.

Differential RSSI Input

The DS1886 offers a fully differential input for RSSI

that enables high-side monitoring of RSSI, as shown in

Figure 3. This reduces board complexity by eliminating

the need for a high-side differential amplifier or a cur-

rent mirror.

Laser Bias and Laser Power Through TXMON

The DS1886 measures both laser bias (TXB) and laser

power (TXP) through the same input pin, TXMON. The

Figure 3. RSSI Differential Input for High-Side RSSI

KRMD[1:0]

TXCTRL3[4:3]

NO. OF RIGHT-SHIFTS

TEMP

VCC

TXB

RSSIC

TOGGLE MON_SEL

RSSIF

TXP

TEMP

tRR

NOTE: IF VCC LO ALARM OR WARNING IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE

THE VCC LO ALARM THRESHOLD.

TOGGLE MON_SEL

RSSIP

RSSIN

ADC

680

Ω

ROSA

VCC

DS1886

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