ADSP-BF607 datasheet(17/44 Pages) AD

17 / 44 page

Preliminary Technical Data

Rev. PrD

Page 17 of 44

March 2012

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

and functional units are idle. Exiting a full system reset starts

with Core-0 only being ready to boot. Exiting a Core-n only

reset starts with this Core-n being ready to boot.

The Reset Control Unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions puts the system into an undefined state or causes

resources to stall. This is particularly important when only one

of the cores is reset (programs must ensure that there is no

pending system activity involving the core that is being reset).

From a system perspective reset is defined by both the reset tar-

get and the reset source as described below.

Target defined:

• Hardware Reset – All functional units are set to their

default states without exception. History is lost.

• System Reset – All functional units except the RCU are set

to their default states.

• Core-n only Reset – Affects Core-n only. The system soft-

ware should guarantee that the core in reset state is not

accessed by any bus master.

Source defined:

• Hardware Reset – The SYS_HWRST input signal is

asserted active (pulled down).

• System Reset – May be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit (Hibernate)

or any of the system event controller (SEC), trigger routing

unit (TRU), or emulator inputs.

• Core-n-only reset – Triggered by software.

• Trigger request (peripheral).

Voltage Regulation

The processor requires an external voltage regulator to power

the VDD_INT pins. To reduce standby power consumption, the

external voltage regulator can be signaled through

SYS_EXTWAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, all external supply pins (VDD_EXT,

VDD_USB, VDD_DMC) can still be powered, eliminating the need for

external buffers. The external voltage regulator can be activated

from this power down state by asserting the SYS_HWRST pin,

which then initiates a boot sequence. SYS_EXTWAKE indicates

a wakeup to the external voltage regulator.

SYSTEM DEBUG

The processor includes various features that allow for easy sys-

tem debug. These are described in the following sections.

System Watchpoint Unit

The System Watchpoint Unit (SWU) is a single module which

connects to a single system bus and provides for transaction

monitoring. One SWU is attached to the bus going to each sys-

tem slave. The SWU provides ports for all system bus address

channel signals. Each SWU contains four match groups of regis-

ters with associated hardware. These four SWU match groups

operate independently, but share common event (interrupt,

trigger and others) outputs.

System Debug Unit

The System Debug Unit (SDU) provides IEEE-1149.1 support

through its JTAG interface. In addition to traditional JTAG fea-

tures, present in legacy Blackfin products, the SDU adds more

features for debugging the chip without halting the core

processors.

EZ-KIT LITE® EVALUATION BOARD

For evaluation of ADSP-BF606/ADSP-BF607/ADSP-

BF608/ADSP-BF609 processors, use the EZ-KIT Lite

® boards

available from Analog Devices. Order using part numbers

ADZS-BF609-EZLITE. The boards come with on-chip emula-

tion capabilities and are equipped to enable software

development. Multiple daughter cards are available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each processor. The emulator

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

ADSP-BF607 Datasheet(PDF) 17 Page - Analog Devices

ADSP-BF607 Datasheet(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL