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DM9161C Datasheet(PDF) 33 Page - Davicom Semiconductor, Inc. |
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DM9161C Datasheet(HTML) 33 Page - Davicom Semiconductor, Inc. |
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33 / 47 page ![]() DM9161C 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 35 Final Version: DM9161C-DS-F01 October 26, 2011 8.12 (Specified config) Register – 20 Bit Bit Name Default Description 20.15 TSTSE1 0,RW Vendor test select control 20.14 TSTSE2 0,RW Vendor test select control 20.13 Reserved 0, RO Reserved Read as 0, ignore on write 20.12 TSTSEL3 0,RW Vendor test select control 20.11 PREAMBLEX 0,RW Preamble Saving Control 1: 10M TX preamble bit count is normal. 0:when bit 10 is set, the 10M TX preamble count is reduced When bit 11 of register 29 is set, 12-bit preamble bit is reduced. Otherwise 22-bit preamble bit is reduced. 20.10 TX10M_PWR 0,RW 10M TX Power Saving Control 1: enable 10M TX power saving 0: disable 10M TX power saving 20.9 NWAY_PWR 0,RW N-Way Power Saving Control 1: disable N-Way power saving 0: enable N-Way power saving 20.8 Reserved 0, RO Reserved Read as 0, ignore on write 20.7 MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 1: MDIX mode 0: MDI mode 20.6 AutoNeg_dpbk 0,RW Auto-negotiation Loopback 1: test internal digital auto-negotiation Loopback 0: normal. 20.5 Mdix_fix Value 0, RW MDIX_CNTL force value: When MDIX_DOWN = 1, MDIX_CNTL value depend on the register value. 20.4 Mdix_do wn 0,RW MDIX Down Manual force MDI/MDIX. 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5 0: Enable HP Auto-MDIX 20.3 MonSel1 0,RW Vendor monitor select 20.2 MonSel0 0,RW Vendor monitor select 20.1 RMII_Ver 0,RW RMII version 1: support RMII 1.0 0: support RMII 1.2 20.0 PD_value 0,RW Power down control value Decision the value of each field Register 19. 1: power down 0: normal |
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