F71872 datasheet(32/115 Pages) FINTEK

32 / 115 page

July, 2007

V0.28P

F71872

6-5 VDDLED_SEL

R/W 2’b11 VDDLED function select, powered by VDD.

00: VDDLED always output low.

01: VDDLED tri-state

10: VDDLED output 0.5Hz clock.

11: VDDLED output 1Hz clock.

( clock output is inverse with VSBLED clock output )

(Powered by VDD)

VDDLED_EN

R/W

VDDLED enable, powered by VDD.

0: the function of PCIRST5#/GP15/VDDLED is PCIRST5#/GP15.

1: the function of PCIRST5#/GP15/VDDLED is VDDLED.

(Powered by VDD)

Reserved

Reserved.

2-1 VSBLED_SEL

R/W 2’b11 VSBLED function select, powered by VSB3V.

00: VSBLED always output low.

01: VSBLED tri-state

10: VSBLED output 0.5Hz clock.

11: VSBLED output 1Hz clock.

(Powered by VSB)

VSBLED_EN

R/W

VSBLED enable, powered by VSB3V.

0: the function of PWROK2/GP25/VSBLED is PWROK2/GP25.

1: the function of PWROK2/GP25/VSBLED is VSBLED.

(Powered by VSB)

7.1.11 Multi Function Select 1 Register

 Index 29h (Powered by VDD)

Bit

Name

R/W Default

Description

RST_DRV_DIS

0: enable PCIRSTx pin driving.

1: disable PCIRSTx pin driving.

Power on trap by DTR2#

6-5 Reserved

Reserved.

F71872 Datasheet(PDF) 32 Page - Feature Integration Technology Inc.

F71872 Datasheet(HTML) 32 Page - Feature Integration Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL