MAG3110

Sensors

Freescale Semiconductor, Inc.

9

3

Modes of Operation

4

Functionality

MAG3110 is a small low-power, digital output, 3-axis linear magnetometer packaged in a 10-pin DFN. The device contains a

4.1

magnetic data readings are available. Interrupt driven sampling allows operation without the overhead of software polling.

4.2

Factory Calibration

MAG3110 is factory calibrated for sensitivity and temperature coefficient. All factory calibration coefficients are applied

automatically by the MAG3110 ASIC before the magnetic field readings are written to registers 0x01 to 0x06 (see section 5).

There is no need for the user to apply the calibration correction in the software and the calibration coefficients are not therefore

accessible to the user.

The magnetic offset registers in addresses 0x09 to 0x0E are not a factory calibration offset but allow the user to define a hard-

iron offset which can be automatically subtracted from the magnetic field readings (see section 4.3.4).

4.3

Digital Interface

4.3.1

bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors (connected to VDDIO)

are expected for both SDA and SCL. When the bus is free, both lines are high.

A transaction on the bus is started through a start condition (START) signal. START condition is defined as a HIGH to LOW

transition on the data line while the SCL line is held HIGH. After START has been transmitted by the Master, the bus is considered

busy. The next byte of data transmitted after START contains the slave address in the first 7 bits, and the eighth bit, the read/

write bit, indicates whether the Master is receiving data from the slave or transmitting data to the save. When an address is sent,

each device in the system compares the first seven bits after a START condition with its own address. If they match, the device

considers itself addressed by the Master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is

the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data

line low so that it remains stable low during the high period of the acknowledge clock period.

Table 7. Modes of Operation Description

Mode

Function Description

STANDBY

Only POR and digital blocks are enabled. Analog subsystem is disabled.

ACTIVE

All blocks are enabled (POR, Digital, Analog).

Table 8. Serial Interface Pin Description

Pin Name

Pin Description

VDDIO

IO voltage

SCL

SDA

INT

Data ready interrupt pin