MPC5554MZP80 datasheet(55/58 Pages) FREESCALE

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Revision History for the MPC5554 Data Sheet

MPC5554 Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Section 3.7, “Power-Up/Down Sequencing

Last paragraph: Changed the first sentence FROM , , , the voltage on the pins goes to high-impedance until . . .

TO. . .the pins go to a high-impedance state until . . .

Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)”

Last sentence: Changed from: ‘This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and

can cause the 1.5 V supply to decrease below its specification, is reset properly.’

To: ‘This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply

to decrease less than its specification, resets correctly.’

Section 4.1, “MPC5553546667 416 PBGA Pinout”

Added the following NOTE before the 416 BGA Map:

NOTE

The MPC5500 devices are pin compatible for software portability and use the primary

function names to label the pins in the BGA diagram. Although some devices do not support

all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those

pins remain available. See the signals chapter in the device reference manual for the signal

muxing.

Table 5 (ESD Ratings ,) ESD Ratings:

Changed footnote 2 from:

• ‘Device failure is defined as: ‘If after exposure to ESD pulses, the device no longer meets the device specification

requirements. Complete DC parametric and functional testing will be performed per applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.’

to:

• Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification

requirements, which includes the complete DC parametric and functional testing at room temperature and hot

temperature.

Table 6 (VRC and POR Electrical Specifications) VCR/POR Electrical Specifications:

• Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5.

On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power

supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,

assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.

• Reformatted columns.

Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications:

• Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and

VDDE3 have a range of 1.6–3.6 V if SIU_ECCR[EBTS] =1.

• Added (TA = TL to TH) to the table title.

Table 14 (Flash Program and Erase Specifications (TA = TL to TH)) Flash Program and Erase Specifications (TA = TL to TH)

• Footnote 1, Changed ‘Typical program and erase times assume nominal supply values and operation at 25 oC’

to ‘Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values..’

Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)

• Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’

Table 19 (Reset and Configuration Pin Timing) Reset and Configuration Pin Timing:

• Footnote 1: Removed VDD = 1.35–1.65 V.

Table 28. Changes Between Rev. 2.0 and 3.0 (continued)

Location

Description of Changes

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