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MPC5554MZP80 Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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MPC5554MZP80 Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 58 page ![]() MPC5554 Microcontroller Data Sheet, Rev. 4 Revision History for the MPC5554 Data Sheet Freescale Semiconductor 56 Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics • Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V. Table 22 (Bus Operation Timing) Bus Operation Timing: • External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts allow for 128 MHz system clock + 2% FM. • Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification. • Specifications 7 and 8: Removed EBI signals BDIP, OE, TSIZ[0:1], WE/BE[0:3]. • Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V. • Footnote 8: Changed EBTS to SIU_ECCR[EBTS]. Table 23 (External Interrupt Timing) External Interrupt Timing (IRQ Signals) • Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V. Table 24 (eTPU Timing) eTPU Timing • Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V. Table 25 (eMIOS Timing) eMIOS Timing • Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V. Table 26 (DSPI Timing’) DSPI Timing: • Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’ • Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts allow for 128 MHz system clock + 2% FM. • Spec 1: SCK cycle time; Changed to 80 MHz minimum column from 25 to 24.4; 112 MHz minimum column from 17.9 to 17.5; 112 MHz maximum column from 2.0 to 2.1. Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics • Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V. Table 28. Changes Between Rev. 2.0 and 3.0 (continued) Location Description of Changes |
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