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MAX5713 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part # MAX5713
Description  Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface
PDF  27 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5713 Datasheet(HTML) 6 Page - Maxim Integrated Products

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Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
MAX5713/MAX5714/MAX5715
6
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage (Note 11)
VIL
2.2V < VDDIO < 5.5V
0.3 x
VDDIO
V
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
Input Leakage Current
IIN
VIN = 0V or VDDIO (Note 11)
Q
0.1
Q
1
F
A
Input Capacitance (Note 10)
CIN
10
pF
DIGITAL OUTPUT (RDY)
Output High Voltage
VOH
VDDIO > 2.5V, ISOURCE = 3mA
VDDIO
- 0.2
V
VDDIO > 1.8V, ISOURCE = 2mA
VDDIO
- 0.2
V
Output Low Voltage
VOL
VDDIO > 2.5V, ISINK = 3mA
0.2
V
VDDIO > 1.8V, ISINK = 2mA
0.2
V
Output Short-Circuit Current
IOSS
ISINK, ISOURCE
±100
mA
SPI TIMING CHARACTERISTICS (CSB, SCLK, DIN, RDY
)
SCLK Frequency
fSCLK
2.7V < VDDIO < 5.5V, standalone,
daisy chain (Note 12)
0
50
MHz
0
20
1.8V < VDDIO < 2.7V, standalone,
daisy chain (Note 12)
0
33
0
20
SCLK Period
tSCLK
2.7V < VDDIO < 5.5V
20
ns
1.8V < VDDIO < 2.7V
30
SCLK Pulse Width High
tCH
8
ns
SCLK Pulse Width Low
tCL
8
ns
CSB Fall to SCLK Fall Setup Time
tCSS0
To first SCLK falling edge
8
ns
CSB Fall to SCLK Fall Hold Time
tCSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0
ns
CSB Rise to SCLK Fall Hold Time
tCSH1
Applies to the 24th SCLK falling edge
0
ns
CSB Rise to SCLK Fall
tCSA
Applies to the 24th SCLK falling edge,
aborted sequence
12
ns
SCLK Fall to CSB Fall
tCSF
Applies to 24th SCLK falling edge
100
ns
CSB Pulse Width High
tCSPW
20
ns
DIN to SCLK Fall Setup Time
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
CLR Pulse Width Low
tCLPW
20
ns
CLR Rise to CSB Fall
tCSC
Required for command to be executed
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
LDAC Fall to SCLK Fall Hold
tLDH
A
pplies to 24th SCLK falling edge,
20
ns



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