CDCM7005-SP datasheet(31/41 Pages) TI1

31 / 41 page

CDCM7005-SP

www.ti.com

SGLS390E – JULY 2009 – REVISED AUGUST 2012

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Hold-Function (Word 3, Bit 9): Selects HOLD function (see more details below).

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Hold-Trigger (Word 3, Bit 11): Defines whether the HOLD function is always activated (Bit 11 = [1]) or whether

it is dependent on the state of the analog PLL lock detect output (Bit 11 = [0]). In the latter case, HOLD is

activated, if lock is set (high) and de-activated if Lock is reset (low).

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Analog PLL Lock Detect (Word 1, Bit 29): Analog lock output charges or discharges an external capacitor with

every valid lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCM7005 supports two types of HOLD functions, one external controllable HOLD mode and one internal

mode, HOLD.

With the external HOLD function the charge pump can directly be switched into 3-state (pin 40 can be

programmed for HOLD [Word 2, Bit 29]). This function is also available via SPI register (Word 2, Bit 31).

If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin is

released, the charge pump is switched back in to normal operation with the next valid reference clock cycle at

PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and all

outputs Yx are at normal operation.

HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to 3-

State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock is

back. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop.

The dedicated looking sequence and a digital phase alignment enable a fast lock.

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CDCM7005-SP Datasheet(PDF) 31 Page - Texas Instruments