LTC4270SLASH datasheet(25/32 Pages) LINER

25 / 32 page

LTC4290/LTC4271

429071f

APPLICATIONS INFORMATION

SERIAL DIGITAL INTERFACE

Overview

The LTC4290/LTC4271 communicates with the host us-

ing a standard SMBus/I2C 2-wire interface. The LTC4290/

LTC4271 is a slave-only device, and communicates with

the host master using the standard SMBus protocols.

Interrupts are signaled to the host via the INT pin. The

Timing Diagrams (Figures 5 through 9) show typical

communicationwaveformsandtheirtimingrelationships.

More information about the SMBus data protocols can be

found at www.smbus.org.

The LTC4290/LTC4271 requires both the VDD and VEEsup-

ply rails to be present for the serial interface to function.

Bus Addressing

The LTC4290/LTC4271’s primary 7-bit serial bus address

is A610A3A2A1A0b, with bit 6 controlled by AD6 and the

lower four bits set by the AD3-AD0 pins; this allows up to

16 LTC4290/LTC4271s, on a single bus. Sixteen LTC4290/

LTC4271 are equivalent to 32 quad PSEs or 128 ports. All

LTC4290/LTC4271salsorespondtothebroadcastaddress

0110000b, allowing the host to write the same command

(typically configuration commands) to multiple LTC4290/

LTC4271s in a single transaction. If the LTC4290/LTC4271

is asserting the INT pin, it will also respond to the alert

responseaddress(0001100b)pertheSMBusspecification.

EachLTC4290/LTC4271islogicallycomposedoftwoquads

of four ports each. Each quad occupies separate, contigu-

ous I2C addresses. The AD6, AD3-0 pins set the address

of the base quad while the second quad is consecutively

numbered. I2C addresses outside of the x10xxxxb range

are considered illegal and will not respond. Each internal

quad is independent of the other quad, with the exception

of writes to the Chip Reset, MSD Inversion and General

Purpose Input Output registers. These registers are global

in nature and will affect all quads.

Figure 14. Example I2C Bus Addressing

Interrupts and SMBAlert

Most LTC4290/LTC4271 port events can be configured

to trigger an interrupt, asserting the INT pin and alerting

the host to the event. This removes the need for the host

to poll the LTC4290/LTC4271, minimizing serial bus traf-

fic and conserving host CPU cycles. Multiple LTC4290/

LTC4271s can share a common INT line, with the host

using the SMBAlert protocol (ARA) to determine which

LTC4290/LTC4271 caused an interrupt.

For information on serial bus usage and device configura-

tion and status, refer to the LTC4271 Software Program-

ming documentation.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However,networksegmentsarenotrequiredtobeisolated

fromeachother,providedthatthesegmentsareconnected

to devices residing within a single building on a single

power distribution system.

LTC4271

AD0

AD1

AD2

AD3

AD6

SCL

SDAIN

SDAOUT

SCL

SDA

AD0

3.3V

AD1

AD2

AD3

AD6

SCL

SDAIN

SDAOUT

I2C ADDRESS

0100000

0100001

LTC4271

I2C ADDRESS

0100111

0101000

429071 F14

LTC4270/ Datasheet(PDF) 25 Page - Linear Technology

LTC4270/ Datasheet(HTML) 25 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL