LTC4270SLASH datasheet(26/32 Pages) LINER

26 / 32 page

LTC4290/LTC4271

429071f

APPLICATIONS INFORMATION

For simple devices such as small PoE switches, the isola-

tion requirement can be met by using an isolated main

power supply for the entire device. This strategy can be

used if the device has no electrically conducting ports

other than twisted-pair Ethernet. In this case, the SDAIN

and SDAOUT pins can be tied together and will act as a

standard I2C/SMBus SDA pin.

If the device is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to

protective ground for some other reason, the Power over

Ethernet subsystem must be electrically isolated from the

rest of the system.

The LTC4290/LTC4271 chipset simplifies PSE isolation by

allowing the LTC4271 chip to reside on the non-isolated

side. There it can receive power from the main logic sup-

ply and connect directly to the I2C/SMBus bus. Isolation

between the LTC4271 and LTC4290 is implemented using

aproprietarytransformer-basedcommunicationprotocol.

Additional details are provided in the Serial Bus Isolation

section of this data sheet.

EXTERNAL COMPONENT SELECTION

Power Supplies and Bypassing

The LTC4290/LTC4271 requires two supply voltages to

operate. VDD requires 3.3V (nominally) relative to DGND.

VEE requires a negative voltage of between –45V and

–57V for Type 1 PSEs or –51V to –57V for Type 2 PSEs,

relative to AGND.

Digital Power Supply

VDD provides digital power for the LTC4271 processor,

and draws a maximum of 15mA. A ceramic decoupling

cap of at least 0.1μF should be placed from VDD to DGND,

as close as practical to each LTC4271 chip. A 1.8V core

voltage supply is generated internally and requires a 1µF

ceramic decoupling cap between the CAP1 pin and DGND.

In the LTC4290/LTC4271, VDD should be delivered by the

host controller’s non-isolated 3.3V supply. To maintain

required isolation AGND and DGND must not be con-

nected in any way.

Main PoE Power Supply

VEE is the main isolated PoE supply that provides power

to the PDs. Because it supplies a relatively large amount

of power and is subject to significant current transients,

it requires more design care than a simple logic supply.

For minimum IR loss and best system efficiency, set VEE

near maximum amplitude (57V), leaving enough margin

to account for transient over or undershoot, temperature

drift, and the line regulation specifications of the particular

power supply used.

Bypass capacitance between AGND and VEE is very im-

portant for reliable operation. If a short circuit occurs at

one of the output ports it can take as long as 1μs for the

LTC4290 to begin regulating the current. During this time

the current is limited only by the small impedances in the

circuit and a high current spike typically occurs, causing a

voltage transient on the VEE supply and possibly causing

the LTC4290/LTC4271 to reset due to a UVLO fault. A 1μF,

100V X7R capacitor placed near the VEE pin along with an

electrolyticbulkcapacitorofatleast47µFisrecommended

to minimize spurious resets.

Serial Bus Isolation

TheLTC4290/LTC4271chipsetusestransformerstoisolate

the LTC4271 from the LTC4290. In this case, the SDAIN

and SDAOUT pins can be shorted to each other and tied

directly to the I2C/SMBus bus. The transformers should

be 10BASE-T or 10/100BASE-T with a 1:1 turns ratio. It

is important that the selected transformers do not have

common-mode chokes. These transformers typically

provide 1500V of isolation between the LTC4271 and the

LTC4290. For proper operation strict layout guidelines

must be met.

LTC4270/ Datasheet(PDF) 26 Page - Linear Technology

LTC4270/ Datasheet(HTML) 26 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL