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MPC5645S Datasheet(PDF) 121 Page - Freescale Semiconductor, Inc |
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MPC5645S Datasheet(HTML) 121 Page - Freescale Semiconductor, Inc |
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121 / 146 page  Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 121 4.18.10 Deserial Serial Peripheral Interface (DSPI) Table 67. DSPI Timing1 1 DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, T A = -40 to 105 °C, and CL = 50 pF with SRC = 0b10. Num Symbol C Characteristic Min Max Unit SpecID 1tSCK CC2 2 Parameter values guaranteed by design. D SCK Cycle TIme3,4 3 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. 4 The actual minimum SCK Cycle Time is limited by pad performance. 605 5 Maximum clock possible is System clock/2. — ns A11.1 2tCSC CC2 D PCS to SCK Delay6 6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2. - — ns A11.2 3tASC CC2 D After SCK Delay7 7 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 20 — ns A11.3 4tSDC CC2 D SCK Duty Cycle tSCK/2 –2ns tSCK/2 + 2ns ns A11.4 5tA CC2 D Slave Access Time (PCSx active to SOUT driven) — 25 ns A11.5 6tDIS CC2 D Slave SOUT Disable Time (PCSx inactive to SOUT High-Z or invalid) — 25 ns A11.6 7tSUI CC2 D Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) 8 This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register. 20 10 5 35 — — — — ns ns ns ns A11.7 8tHI CC2 D Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) –4 10 26 –4 — — — — ns ns ns ns A11.8 9tSUO CC2 D Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) — — — — 15 20 30 15 ns ns ns ns A11.9 10 tHO CC2 D Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) –15 5.5 0 –15 — — — — ns ns ns ns A11.10 |
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