MPC5645S datasheet(117/146 Pages) FREESCALE

117 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

117

td terminated at the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR2 input capacitance. See

(Figure 32. "SSTL_18 CLass II Test Load").

Figure 32. SSTL_18 CLass II Test Load

4.18.5.3

1.8V LPDDR

Table 62. 1.8V LPDDR DC Specifications

Note that the final JEDEC LPDDR SDRAM specifications (JESD79-4) for LPDDR operation supersedes any specification in

this document.

The SSTL_18 output with ipp_sre[2:0] set to enabling 1.8V LPDDR mode, at the destination, have a rise/fall time (10%-90%)

between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated

at the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR input capacitance. See Figure 27.

Symbol C

Parameter

Condition

Min

Nom

Max

Unit

Notes

SpecID

vddet

I/O Supply Voltage

—

1.7

1.8

1.9

JESD79-4

A5.27

vdd

Core Supply Voltage

—

1.08

1.2

1.32

—

A5.28

Data Inputs (DQ, DM, DQS)

A5.29

Vih(dc)

C DC Input Logic High

—

vddet*0.7

—

vddet+0.3

JESD79-4

A5.30

Vil(dc)

C DC Input Logic Low

—

-0.3

—

vddet*0.3

JESD79-4

A5.31

Vih(ac)

C AC Input Logic High

—

vddet*0.8

—

vddet+0.3

JESD79-4

A5.32

Vil(ac)

C AC Input Logic low

—

-0.3

—

vddet*0.2

JESD79-4

A5.33

Data Outputs (DQ, DQS)

A5.34

Voh

C Output High Voltage

Level

Ioh=-0.1mA

vddet*0.9

—

JESD79-4

A5.35

Vol

C Output Low Voltage

Level

Iol=0.1mA

—

vddet*0.1

JESD79-4

A5.36

PAD

ipp_do

Z0=70 td= 0.167ns

4pF

Vtt

pad_st/pad_st_odt

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