MPC5645S datasheet(140/146 Pages) FREESCALE

140 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

140

Freescale Semiconductor

Revision history

Table 74. Revision history

Revision

(Date)

Description

(06 Oct 2009)

Initial release.

(7 Dec 2009)

Editorial changes.

Extensive modifications throughout the “Pinout and signal descriptions” section.

Revised the “Absolute maximum ratings” table.

Revised the “Recommended operating conditions (3.3 V)” table.

Revised the “Recommended operating conditions (5 V)” table.

In the “Voltage regulator electrical characteristics” section, changed “NJD2783” to NJD2873”.

Revised the “Interface to TFT LCD panels” section.

(3 Mar 2010)

Editorial changes.

Added the RoHS logo (indicating RoHS compliance).

Added a "SpecID" column to specification tables throughout the document.

In the device-comparison table:

• Revised the “Timed I/O” entry.

• Changed “Nexus 3” to “Nexus Class 3”.

In the feature list:

• Revised the information for the TCON and RSDS interface.

• In the ADC entry, changed “20 internal channels” to “Up to 20 internal channels”.

• In the QuadSPI entry, changed “quad modes of operation” to “quad IO serial flash memory”.

• In the DCU3 and DCULite entry, changed “WVGA” to “XGA”.

In the “Feature details” section:

• Revised some module abbreviations and names to be consistent with the rest of the documentation.

• In the GFX2D section, deleted “and Adobe Flash 7”.

• In the QuadSPI section, changed “Maximum frequency 80 MHz” to “Maximum serial clock

frequency 80 MHz”

• In the FlexCAN section, changed “The FlexCan modules offer” to “Each FlexCAN module offers”.

• In the DCULite section, changed “WVGA” to “XGA”.

In the 176-pin pinout, changed “MDD” to “MDO”.

In the 208-pin pinout:

• For pin 105, changed “VDDE” to “VDDE_B”.

• Renamed pin 145 (was VRSDS, is VREF_RSDS”)

• For pin 148, changed “RSRS3+P” to “RSDS3P”.

• For pin 160, changed “SCL_D” to “SCL_3”.

• For pin 161, changed “SDA_D” to “SDA_3”.

• For pin 178, changed “DCULITE_G8” to “DCULITE_G6”.

In the 324-pin pinout:

• Renamed pin A1 (was VSS_DR, is VSS).

• Renamed pin B2 (was VDDE_DDR, is VDD_DR).

• Renamed pins D11 and J9 (were VDD33_DR, are VDDE_B).

Added the “Pad configuration during reset phases” section.

In the “Voltage supply pin descriptions” table:

• Renamed VRSDS to VREF_RSDS and added a footnote about the pin’s required termination.

• Added pin B2 to VDD_DR in the 324-pin package.

• Moved pins D11 and J9 to VDDE_B.

Revised the “System pin descriptions” table.

Replaced the entire “DRAM interface pin summary” table.

• In the “Nexus pins” table, added a PCR column.

MPC5645S Datasheet(PDF) 140 Page - Freescale Semiconductor, Inc

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