MPC5645S datasheet(141/146 Pages) FREESCALE

141 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

141

3 (continued)

(3 Mar 2010)

Added the “VIU muxing” section.

Added the “System design information” section and a “Power-up sequencing” subsection.

In the “Recommended operating conditions (3.3 V)” table, revised footnotes 2 and 4.

In the “Recommended operating conditions (5.0 V)” table, revised footnotes 3 and 5.

Revised the text in the “Voltage regulator electrical characteristics” section.

Added meaningful content to the “DC electrical characteristics” section.

In the “Reset electrical characteristics” table, changed the specifications for WFRST (was max 40 ns, is

max 70 ns) and WNFRST (was min 1000 ns, is min 400 ns).

Replaced the entire “Pad AC specifications” section.

Added meaningful content to the “Video Input Unit timing” section.

Added orderable part numbers.

Revised the “Commercial product code structure” figure.

(24 Jun 2010)

Editorial changes and improvements.

In the device-comparison table, changed the GPIO count for the 176-pin package (was 127, is 128).

In the feature list:

• Changed “4 KB, 2-way instruction cache” to “4 KB, 2/4-way instruction cache”.

• Changed “32 kHz crystal oscillator” to “32 KHz crystal oscillator”.

• Changed “188 peripheral interrupt sources” to “181 peripheral interrupt sources”.

• Changed “Primary FMPLL” to “Primary FMPLL (FMPLL0)”.

• Changed “Auxiliary FMPLL” to “Auxiliary FMPLL (FMPLL1)”.

• In the crossbar switch description, deleted the reference to AMBA.

• In the SGM description, changed “WAV file” to “PCM wave”.

• Revised the RLE decoder description.

• In the SIUL description, deleted “resets”.

• In the CMU section, changed “PLL” to “primary FMPLL (FMPLL0)”.

In the feature details:

• Changed “32 kHz oscillator” to “32 KHz oscillator”.

• Changed “128 KHz oscillator” to “128 kHz oscillator”.

• Revised the “Low-power operation” section.

• In the ADC section, changed “0 to 5V common mode conversion range” to “0–5 V or 0–3.3 V

common mode conversion range”.

• Revised the DCU3 section.

• In the “On-chip graphics SRAM” section, added an entry for independent data buffers.

• In the MPU section, changed “Protection offered for 3 concurrent read ports” to “Protection offered

for 4 concurrent read ports”.

In the 176-pin pinout:

• Added content to indicate which functions are available only in this package.

• For pin 116, changed PD113 to PDI13.

• For pin 117, changed PD114 to PDI14.

• For pin 1, changed DCU_VSYNC_TCON2 to DCU_VSYNC.

• For pin 2, changed DCU_HSYNC_TCON1 to DCU_HSYNC.

• For pin 3, changed DCU_DE_TCON3 to DCU_DE.

• For pin 16, changed DCU_TAG_TCON3 to DCU_TAG.

• For pin 56, changed PDI0(VIU0) to PDI0_VIU0.

• For pin 57, changed PD11(VIU1) to PDI1_VIU1.

• For pin 58, changed PDI12(VIU2) to PDI2_VIU2.

• For pin 59, changed PDI3(VIU3) to PDI3_VIU3.

• For pin 148, deleted TCON0.

• For pin 155, deleted DCULITE_G7.

Table 74. Revision history (continued)

Revision

(Date)

Description

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