40mV

VCC1

VCC2

SDA1

GND1

GND2

SDA2

A

B

D

C

ISO1540

50mV

From Master to Slave

From Slave to Master

S Slave Address R A

DATA

A

DATA

A P

S Slave Address W A

DATA

A

DATA

A P

Master Transmitter writing to Slave Receiver

Master Receiver reading from Slave Transmitter

A = acknowledge

A = not acknowledge

S = Start

P = Stop

R = Read

W = Write

ISO1540

ISO1541

www.ti.com

SLLSEB6 – JULY 2012

The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a

high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA

while SCL is high.

If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the

master is in master-transmit mode and the slave is in slave-receive mode.

If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the

receipt of every byte but the last one (see Figure 8). In this situation the master is in master-receive mode and

the slave is in slave-transmit mode.

The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for

further transfers.

Figure 8. Transmit or Receive Mode Changes During a Data Transfer

When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when

receiving acknowledgment from the slave.

When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending

a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a

transaction.

Note, that the master ends a reading sequence by not acknowledging (NACK) the last byte received. This

procedure resets the slave state machine and allows the master to send the STOP command.

Isolator Functional Principle

To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two

unidirectional signal lines, each of which is isolated via a single-channel digital isolator. Each channel output is

capacitance.

Figure 9. SDA Channel Design and Voltage Levels at SDA1

At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.

However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode

drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The

comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V

maximum driven directly by SDA1 and the buffered output low-level of B.

Copyright © 2012, Texas Instruments Incorporated

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Product Folder Link(s): ISO1540 ISO1541