TNETX15VE datasheet(49/113 Pages) TI1

49 / 113 page

TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

receive block register, RXblock at 0xF6–0xF7 (DIO)

BYTE 1

BYTE 0

BIT

Reserved

RXblock

Initial Values After Reset

The RXblock register blocks frame reception, depending on the port from which the frame originated. Frames

arriving on ports whose corresponding bit is set to on1 are discarded. The RXblock register can be overridden

if the packet destination address has the NBLCK bit set to 1.

attached microprocessor’s define/routing register, CPUTX at 0xF8 (DIO)

BIT

CPU PORT

TX ROUTING CODE

Initial Values After Reset

BIT

NAME

FUNCTION

7–4

CPU PORT

Attached microprocessor port assignment. CPU PORT specifies the port where the CPU is attached. Code

0xF is reserved and is ignored.

3–0

TX ROUTING CODE

Transmit routing code. TX ROUTING CODE specifies where frames coming from the CPU port are routed.

This field has the following behavior:

• If this field is 0xF, the CPU routing function is disabled and frames are routed according to the

TNETX15VE lookup table.

• If this field is not 0xF, frames that come from the port specified in CPU PORT are routed to the port

encoded in TX ROUTING CODE, by passing any routing from the destination address lookup.

After the frame has been transmitted using this register, it disables itself by writing a 0xF to this field.

The CPUTX register allows the programmer to specify where frames coming from the CPU should be

forwarded. The CPU port is specified in the CPU PORT field and frames are routed to the port specified in the

TX ROUTING CODE. While useful in replying to BPDUs in spanning tree when ports are normally blocked, this

mechanism can be used at any time to specifically route one packet.

TNETX15VE Datasheet(PDF) 49 Page - Texas Instruments