TNETX15VE datasheet(96/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Note 8 and Figure 21)

DRAM interface

NO.

MIN

MAX

UNIT

tsu(DD)

Setup time, DD35–DD0 valid before OSCIN

↑

tsu(DWE)

Setup time, from DWE

↓ to OSCIN↑

tsu(DRAS)

Setup time, from DRAS

↓ to OSCIN↑

tsu(DCAS)

Setup time, from DCAS

↓ to OSCIN↑

th(DD)

Hold time, DD35–DD0 valid after OSCIN

↑

th(DWE)

Hold time, DWE low after OSCIN

↑

th(DRAS)

Hold time, DRAS low after OSCIN

↑

th(DCAS)

Hold time, DCAS low after OSCIN

↑

NOTE 8: The TNETX15VE monitors the DRAM interface to extract frame information. The TNETX15VE extracts information on only the write

cycles. The TNETX15VE does not output any signals to the DRAM interface. The only parameters that apply to the TNETX15VE on

this interface are delay times, with respect to OSCIN, that translate into the TNETX15VE setup times. The TNETX15VE implements

internal delay elements to ensure its setup requirements.

OSCIN

(input)

Data

DWE

(input)

DRAS

(input)

DCAS

(input)

DD35–DD0

(input)

TNETX15VE Latches Here

Figure 21. DRAM Interface Timing

TNETX15VE Datasheet(PDF) 96 Page - Texas Instruments

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