TNETX15VE datasheet(11/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

DIO interface

statistics interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

EINT

112

TNETX15VE interrupt. EINT is an interrupt request from the TNETX15VE to an optional attached

microprocessor. Its purpose is to reduce the polling that is required for the processor to be current on the

operational states of the TNETX15VE. The interrupt cause is determined by reading the interrupt register

(0x28, 0x29). It is not required to acknowledge or act on the interrupts (unmanaged operation). EINT is

active high and level sensitive; it is high when any of the interrupt triggers are active.

ESCS

TNETX15VE chip select. When ESCS is active (low), a port access is valid for the TNETX15VE device.

ESCS must not be tied to any other chip-select signal (such as the TNETX3150/TNETX3150A SCS).

SAD1

SAD0

DIO address bus. SAD1–SAD0 selects the TNETX15VE host registers.

SAD1

DESCRIPTION

DIO address low

SAD0

DIO address high

DIO data

DIO data auto-increment

SDATA7†

SDATA6

SDATA5

SDATA4

I/O

DIO data bus SDATA7 SDATA0 is a byte wide bidirectional DIO bus

SDATA3

I/O

DIO data bus. SDATA7–SDATA0 is a byte-wide bidirectional DIO bus.

SDATA2

SDATA1

SDATA0‡

SRDY

DIO ready. When SRDY is active low, the following conditions occur:

– When SRNW = 1, the interface host is told that data is valid for reading by the host.

– When SRNW = 0, the interface host is told that data has been received by the TNETX15VE. When

ESCS is inactive (high), SRDY is disabled [high-impedance (Z) state]. For this reason, SRDY

should have a 10-K pullup resister to avoid engaging the hosts ready logic during the time when

TNETX15VE is not addressed.

SRNW

DIO read/not write. SRNW is a read- or write-select signal.

– When SRNW is high, the read operation is performed by the host.

– When SRNW is low, the write operation is performed by the host.

† Most-significant bit

‡ Least-significant bit

DIO interface

MII

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

MDCLK

113

MII management data clock. MDCLK is a clock from the TNETX15VE for the serial MII management data

MDIO. MDCLK can be disabled [high-impedance (Z) state] by MDIOEN [a bit in the SIO register at 0x0A

(DIO)].

MDIO

109

I/O

MII management data input/output. MDIO is the data terminal for serial MII management data. MDIO

requires an external pullup resistor for proper operation. MDIO can be disabled [high-impedance (Z) state]

by MDIOEN [a bit in the SIO register at 0x0A (DIO)].

MRESET

114

MII management reset. MRESET is a reset signal for the serial MII management interface. MRESET can

be disabled [high-impedance (Z) state] by MDIOEN [a bit in the SIO register at 0x0A (DIO)].

TNETX15VE Datasheet(PDF) 11 Page - Texas Instruments

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