Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

VLPR (Very Low

Power Run)

On-chip voltage regulator is in a low power mode that supplies only

enough power to run the chip at a reduced frequency. Reduced

frequency Flash access mode (1 MHz); LVD off; in BLPI clock mode,

the fast internal reference oscillator is available to provide a low power

nominal 4MHz source for the core with the nominal bus and flash clock

required to be <800kHz; alternatively, BLPE clock mode can be used

with an external clock or the crystal oscillator providing the clock

source.

Run

—

VLPW (Very

Low Power

Wait) -via WFI

Same as VLPR but with the core in sleep mode to further reduce

power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip

voltage regulator is in a low power mode that supplies only enough

power to run the chip at a reduced frequency.

Sleep

Interrupt

VLPS (Very Low

Power Stop)-via

WFI

Places chip in static state with LVD operation off. Lowest power mode

with ADC and pin interrupts functional. Peripheral clocks are stopped,

but OSC, LPTMR, RTC, CMP, TSI can be used. TPM and UART can

optionally be enabled if their clock source is enabled. NVIC is disabled

(FCLK = OFF); AWIC is used to wake up from interrupt. On-chip

voltage regulator is in a low power mode that supplies only enough

power to run the chip at a reduced frequency. All SRAM is operating

(content retained and I/O states held).

Sleep Deep

Interrupt

LLS (Low

Leakage Stop)

State retention power mode. Most peripherals are in state retention

mode (with clocks stopped), but OSC, LLWU, LPTMR, RTC, CMP,,

TSI can be used. NVIC is disabled; LLWU is used to wake up.

NOTE: The LLWU interrupt must not be masked by the interrupt

controller to avoid a scenario where the system does not fully

exit stop mode on an LLS recovery.

All SRAM is operating (content retained and I/O states held).

Sleep Deep

Wakeup

Interrupt1

VLLS3 (Very

Low Leakage

Stop3)

Most peripherals are disabled (with clocks stopped), but OSC, LLWU,

LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used

to wake up.

SRAM_U and SRAM_L remain powered on (content retained and I/O

states held).

Sleep Deep

Wakeup Reset2

VLLS1 (Very

Low Leakage

Stop1)

Most peripherals are disabled (with clocks stopped), but OSC, LLWU,

LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used

to wake up.

All of SRAM_U and SRAM_L are powered off.

Sleep Deep

Wakeup Reset2

VLLS0 (Very

Low Leakage

Stop 0)

Most peripherals are disabled (with clocks stopped), but LLWU,

LPTMR, RTC, TSI can be used. NVIC is disabled; LLWU is used to

wake up.

All of SRAM_U and SRAM_L are powered off.

LPO shut down, optional POR brown-out detection

Sleep Deep

Wakeup Reset2

1. Resumes normal run mode operation by executing the LLWU interrupt service routine.

2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.

Power modes

KL24/KL25 Product Brief, Rev. 2, 6/2012

Freescale Semiconductor, Inc.

Preliminary

19

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