Table 4. KL25 48MHz performance table (continued)

MC Part number

Low Power UART

1

1

1

1

1

1

1

1

1

1

1

1

UART

2

2

2

2

2

2

2

2

2

2

2

2

SPI chip selects per

module

1/1

1/1

1/1

1/1

1/1

1/1

1/1

1/1

1/1

1/1

1/1

1/1

I2C

2

2

2

2

2

2

2

2

2

2

2

2

USB OTG LS/FS w/ on-

chip xcvr

1

1

1

1

1

1

1

1

1

1

1

1

USB 120mAReg

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

Human-Machine Interface

Segment LCD

-

-

-

-

-

-

-

-

-

-

-

-

TSI (Capacitive Touch)

9ch

9ch

9ch

14ch

14ch

14ch

16ch

16ch

16ch

16ch

16ch

16ch

Total GPIOs

23

23

23

36

36

36

50

50

50

66

66

66

GPIOs w/ Interrupt

12

12

12

16

16

16

19

19

19

23

23

23

High Current GPIOs

(18mA)

2

2

2

4

4

4

4

4

4

4

4

4

Operating Characteristics

Voltage Range

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

1.71-3.

6V

Flash Write V

1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V

Temp Range

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

-40 to

105C

4.5 Module-by-module feature list

The following sections describe the high-level module features for the family's superset device. See the previous section for

differences among the subset devices.

Core Modules

4.5.1.1 ARM Cortex M0+ Core

• Up to 48 MHz core frequency from 1.71 V to 3.6 V across temperature range of –40 °C to 105 °C

• Support up to 32 interrupt request sources

• 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per

instruction)

• Binary compatible instruction set architecture with the CM0 core

4.5.1

Core Modules

KL24/KL25 Product Brief, Rev. 2, 6/2012

12

Preliminary

Freescale Semiconductor, Inc.

General Business Information