4.5.6.4 UART1 to UARTx

• Full-duplex, standard non-return-to-zero (NRZ) format

• Double-buffered transmitter and receiver with separate enables

• Programmable baud rates (13-bit modulo divider)

• Interrupt-driven or polled operation:

• Transmit data register empty and transmission complete

• Receive data register full

• Receive overrun, parity error, framing error, and noise error

• Idle receiver detect

• Active edge on receive pin

• Break detect supporting LIN

• Hardware parity generation and checking

• Programmable 8-bit or 9-bit character length

• Programmable 1-bit or 2-bit stop bits

• Receiver wakeup by idle-line or address-mark

• Optional 13-bit break character generation / 11-bit break character detection

• Selectable transmitter output polarity

4.5.6.5 UART0

• Full-duplex operation

• Standard mark/space non-return-to-zero (NRZ) format

• 13-bit baud rate selection with fractional divide of 32

• Programmable 8-bit or 9-bit data format

• Separately enabled transmitter and receiver

• Programmable transmitter output polarity

• Programmable receive input polarity

• 13-bit break character option

• 11-bit break character detection option

• Two receiver wakeup methods:

• Idle line wakeup

• Address mark wakeup

• Address match feature in receiver to reduce address mark wakeup ISR overhead

• Interrupt or DMA driven operation

• Receiver framing error detection

• Hardware parity generation and checking

• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection

• Operation in low power modes

4.5.6.6 Serial Peripheral Interface (SPI)

• Master and slave mode

• Full-duplex, three-wire synchronous transfers

• Programmable transmit bit rate

• Double-buffered transmit and receive data registers

• Serial clock phase and polarity options

• Slave select output

• Mode fault error flag with CPU interrupt capability

• Control of SPI operation during wait mode

• Selectable MSB-first or LSB-first shifting

• Support for both transmit and receive by DMA

Communication Interfaces

KL24/KL25 Product Brief, Rev. 2, 6/2012

Freescale Semiconductor, Inc.

Preliminary

17

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