The RST input clears the serial interface in case of a

hung bus, terminating any serial transaction to or from

the MAX7320.

When the MAX7320 is read through the serial interface,

the actual logic states at the ports are read back.

Output port power-up logic states are selected by the

address select inputs AD0 and AD2. Ports default to

logic-high or logic-low on power-up in groups of four

(see Table 3).

RST Input

condition. A reset does not change the contents of the

output register. RST is overvoltage tolerant to +5.5V.

Standby Mode

When the serial interface is idle, the MAX7320 automat-

ically enters standby mode, drawing minimal supply

current.

Slave Address and Power-Up

Default Logic States

Address inputs AD0 and AD2 determine the MAX7320

slave address and set the power-up output logic states.

Power-up logic states are set in groups of four (see

Table 3). The MAX7320 uses a different range of slave

addresses (101xxxx) than the MAX7319, MAX7321,

MAX7322, and MAX7323 (110xxxx).

transmission, regardless of whether the transmission is

actually addressing the MAX7320. The MAX7320 distin-

guishes whether address inputs AD0 and AD2 are con-

nected to SDA or SCL instead of fixed logic levels V+

or GND during this transmission. This means that the

MAX7320 slave address can be configured dynamical-

ly in the application without cycling the device supply.

On initial power-up, the MAX7320 cannot decode the

transmission. AD0 and AD2 initially appear to be con-

nected to V+ or GND. This is important because the

address selection determines the power-up logic levels

and SCL bus interface lines are high impedance at the

pins of every device (master or slave) connected to the

bus, including the MAX7320. This is guaranteed as part

and AD2 that are connected to SDA or SCL normally

appear at power-up to be connected to V+. The power-

up output state selection logic uses AD0 to select the

power-up state for ports O3–O0, and uses AD2 to

select the power-up state for ports O7–O4. The rule is

that a logic-high, SDA, or SCL connection selects a

_______________________________________________________________________________________

7

PIN

CONNECTION

DEVICE ADDRESS

OUTPUTS POWER-UP DEFAULT

AD2

AD0

A6

A5

A4

A3

A2

A1

A0

O7

O6

O5

O4

O3

O2

O1

O0

SCL

GND

101

000

011

110

000

SCL

V+

101

000

111

111

111

SCL

SCL

101

001

011

111

111

SCL

SDA

101

001

111

111

111

SDA

GND

101

010

011

110

000

SDA

V+

101

010

111

111

111

SDA

SCL

101

011

011

111

111

SDA

SDA

101

011

111

111

111

GND

GND

101

100

000

000

000

GND

V+

1

0

1

100

100

001

111

GND

SCL

101

101

000

001

111

GND

SDA

101

101

100

001

111

V+

GND

101

110

011

110

000

V+

V+

101

110

111

111

111

V+

SCL

101

111

011

111

111

V+

SDA

101

111

111

111

111

Table 3. MAX7320 Address Map