Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9

bits. The master generates the ninth clock pulse, and

the recipient pulls down SDA during the acknowledge

clock pulse, such that the SDA line is stable low during

the high period of the clock pulse. When the master is

transmitting to the MAX7320, the device generates the

acknowledge bit because the MAX7320 is the recipi-

ent. When the MAX7320 is transmitting to the master,

the master generates the acknowledge bit because the

master is the recipient.

Slave Address

The MAX7320 has a 7-bit slave address (Figure 5). The

8th bit following the 7-bit slave address is the R/W bit. It is

low for a write command, and high for a read command.

The 1st (A6), 2nd (A5), and 3rd (A4) bits of the

MAX7320 slave address are always 1, 0, and 1.

select the slave address bits A3, A2, A1, and A0. The

MAX7320 has 16 possible slave addresses (Table 3),

addresses from the MAX7319, MAX7321, MAX7322 and

MAX7323, for which 1st (A6), 2nd (A5), and 3rd (A4)

bits of the slave address are always 1, 1, and 0.

Accessing the MAX7320

A single-byte read from the MAX7320 returns the sta-

tus of the eight output ports, read back as inputs.

A 2-byte read repeatedly returns the status of the eight

output ports, read back as inputs.

STOP bit) repeatedly returns the status of the eight out-

put ports, read back as inputs.

A single-byte write to the MAX7320 sets the logic state

of all eight outputs.

A multibyte write to the MAX7320 repeatedly sets the

logic state of all eight outputs.

Reading from the MAX7320

A read from the MAX7320 starts with the master trans-

mitting the MAX7320’s slave address with the R/W bit

set high. The MAX7320 acknowledges the slave

address, and samples the logic state of the output

ports during the acknowledge bit. The master can read

one or more bytes from the MAX7320 and then issue a

STOP condition (Figure 6). The MAX7320 transmits the

current port data, read back from the actual port out-

puts (not the port output latches) during the acknowl-

edge. If a port is forced to a logic state other than its

programmed state, the read back reflects this. If driving

a capacitive load, readback port level verification algo-

rithms may need to take the RC rise/fall time into

account.

Typically, the master reads one byte from the MAX7320,

then issues a STOP condition (Figure 6). However, the

master can read 2 or more bytes from the MAX7320,

then issue a STOP condition. In this case, the MAX7320

resamples the port outputs during each acknowledge

and transmits the new data each time.

Writing to the MAX7320

A write to the MAX7320 starts with the master transmit-

ting the MAX7320’s slave address with the R/W bit set

low. The MAX7320 acknowledges the slave address

and samples the ports during the acknowledge bit. The

master can transmit one or more bytes of data. The

MAX7320 acknowledges each subsequent byte of data

and updates the output ports until the master issues a

STOP condition (Figure 7).

_______________________________________________________________________________________

9

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 3. Bit Transfer

SCL

SDA BY

TRANSMITTER

CLOCK PULSE

FOR ACKNOWLEDGMENT

START

CONDITION

SDA BY

RECEIVER

12

89

S

Figure 4. Acknowledge