SN54LS224A, SN74LS224A

16

× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

WITH 3-STATE OUTPUTS

SDLS023E – JANUARY 1991 – REVISED APRIL 2003

2

POST OFFICE BOX 655303

CLR

EN5

1

OE

CT = 0

9

1D

4

D0

5

D1

6

D2

7

D3

Q0

13

Q1

12

Q2

11

Q3

10

IR

2

2

3

LDCK

CT < 16

&

+ /C1

Z2

CT > 0

&

–

Z3

OR

14

3

CT = 0

&

V4

2

4, 5

CTR

FIFO 16

× 4

15

UNCK

† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate, but does

not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory as if it were controlled by

a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.

Pin numbers shown are for the J and N packages.