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74LS224 Datasheet(PDF) 3 Page - Texas Instruments |
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74LS224 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 13 page ![]() SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023E – JANUARY 1991 – REVISED APRIL 2003 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1 9 3 15 4 5 6 7 2 14 13 12 11 10 OE CLR LDCK UNCK D0 D1 D2 D3 IR OR Q0 Q1 Q2 Q3 16 16 16 16 Ring Counter CTR DIV 16 Write Address Ring Counter CTR DIV 16 Read Address COMP RAM 16 × 4 + CT = 1 + CT = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P Q 1A 2A C5 1 16 EN ≥1 1A,5D 2A 1 16 S 1D C1 S 2D C2 R 3D C3 R 4D C4 Q=P+1 P=Q+1 P=Q EMPTY Pin numbers shown are for the J and N packages. |
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