CYUSB301X datasheet(23/40 Pages) CYPRESS

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CYUSB301X

Document Number: 001-52136 Rev. *L

Page 23 of 40

Note

5. All parameters guaranteed by design and validated through characterization.

Table 11. GPIF II Timing in Asynchronous Mode[5]

Note The following parameters assume one state transition

Parameter

Description

Min

Max

Units

tDS

Data In to DLE setup time. Valid in DDR async mode.

2.3

–

tDH

Data In to DLE hold time. Valid in DDR async mode.

–

tAS

Address In to ALE setup time

2.3

–

tAH

Address In to ALE hold time

–

tCTLassert

CTL I/O asserted width for CTRL inputs without DQ input

association and for outputs.

7–

tCTLdeassert

CTL I/O deasserted width for CTRL inputs without DQ

input association and for outputs.

7–

tCTLassert_DQassert

CTL asserted pulse width for CTL inputs that signify DQ

inputs valid at the asserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

–

tCTLdeassert_DQassert

CTL deasserted pulse width for CTL inputs that signify DQ

input valid at the asserting edge but do not employ in-built

latches (ALE/DLE) for those DQ inputs.

7–

tCTLassert_DQdeassert

CTL asserted pulse width for CTL inputs that signify DQ

inputs valid at the deasserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

7–

tCTLdeassert_DQdeassert

CTL deasserted pulse width for CTL inputs that signify DQ

inputs valid at the deasserting edge but do not employ

in-built latches (ALE/DLE) for those DQ inputs.

–

tCTLassert_DQlatch

CTL asserted pulse width for CTL inputs that employ

in-built latches (ALE/DLE) to latch the DQ inputs. In this

non-DDR case, in-built latches are always close at the

deasserting edge.

7–

tCTLdeassert_DQlatch

CTL deasserted pulse width for CTL inputs that employ

in-built latches (ALE/DLE) to latch the DQ inputs. In this

non-DDR case, in-built latches always close at the

deasserting edge.

–

tCTLassert_DQlatchDDR

CTL asserted pulse width for CTL inputs that employ

in-built latches (DLE) to latch the DQ inputs in DDR mode.

–

tCTLdeassert_DQlatchDDR

CTL deasserted pulse width for CTL inputs that employ

in-built latches (DLE) to latch the DQ inputs in DDR mode.

–

tAA

DQ/CTL input to DQ output time when DQ change or CTL

change needs to be detected and affects internal updates

of input and output DQ lines.

–30

tDO

CTL to data out when the CTL change merely enables the

output flop update whose data was already established.

–25

tOELZ

CTL designated as OE to low-Z. Time when external

devices should stop driving data.

0–

tOEHZ

CTL designated as OE to high-Z

tCLZ

CTL (non-OE) to low-Z. Time when external devices

should stop driving data.

0–

tCHZ

CTL (non-OE) to high-Z

tCTLalpha

CTL to alpha change at output

–

tCTLbeta

CTL to beta change at output

–

tDST

Addr/data setup when DLE/ALE not used

–

tDHT

Addr/data hold when DLE/ALE not used

–

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