CYUSB301X datasheet(30/40 Pages) CYPRESS

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CYUSB301X

Document Number: 001-52136 Rev. *L

Page 30 of 40

Note

8. All parameters guaranteed by design and validated through characterization.

Table 14. I2C Timing Parameters[8]

Parameter

Description

Min

Max

Units

I2C Standard Mode Parameters

fSCL

SCL clock frequency

100

kHz

tHD:STA

Hold time START condition

–

µs

tLOW

LOW period of the SCL

4.7

–

µs

tHIGH

HIGH period of the SCL

–

µs

tSU:STA

Setup time for a repeated START condition

4.7

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

250

–

Rise time of both SDA and SCL signals

–

1000

Fall time of both SDA and SCL signals

–

300

tSU:STO

Setup time for STOP condition

–

µs

tBUF

Bus free time between a STOP and START condition

4.7

–

µs

tVD:DAT

Data valid time

–

3.45

µs

tVD:ACK

Data valid ACK

–

3.45

µs

tSP

Pulse width of spikes that must be suppressed by input filter

n/a

I2C Fast Mode Parameters

fSCL

SCL clock frequency

400

kHz

tHD:STA

Hold time START condition

0.6

–

µs

tLOW

LOW period of the SCL

1.3

–

µs

tHIGH

HIGH period of the SCL

0.6

–

µs

tSU:STA

Setup time for a repeated START condition

0.6

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

100

–

Rise time of both SDA and SCL signals

–

300

Fall time of both SDA and SCL signals

–

300

tSU:STO

Setup time for STOP condition

0.6

–

µs

tBUF

Bus free time between a STOP and START condition

1.3

–

µs

tVD:DAT

Data valid time

–

0.9

µs

tVD:ACK

Data valid ACK

–

0.9

µs

tSP

Pulse width of spikes that must be suppressed by input filter

I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2 V)

fSCL

SCL clock frequency

1000

kHz

tHD:STA

Hold time START condition

0.26

–

µs

tLOW

LOW period of the SCL

0.5

–

µs

tHIGH

HIGH period of the SCL

0.26

–

µs

tSU:STA

Setup time for a repeated START condition

0.26

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

–

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