MMPF0100 datasheet(29/136 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Power Generation

7.4.1.2

OFF Mode

The PF0100 enters the Off mode after a turn-off event. A thermal shutdown event also forces the PF0100 into the Off mode. Only

VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required.

RESETBMCU is asserted, LOW, in this mode.

7.4.1.3

Standby Mode

• Depending on STANDBY pin configuration, Standby is entered when the STANDBY pin is asserted. This is typically used

for low-power mode of operation.

• When STANDBY is de-asserted, Standby mode is exited.

A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level

control of going in and out of such deep sleep modes (DSM).

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing

the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is pre-

programmed through the I2C interface.

Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will

take into account the programmed input polarity as shown in Table 22. When the PF0100 is powered up first, regulator settings

for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active

Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For

simplicity, STANDBY will generally be referred to as active high throughout this document.

Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and

respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This

allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate

seamless entering into Standby mode.

When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY will delay the Standby initiated response for the entire IC,

until the STBYDLY counter expires.

An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.

Table 22. Standby Pin and Polarity Control

STANDBY (Pin)(26)

STANDBYINV (I2C bit)(27)

STANDBY Control (25)

Notes

25.

STANDBY = 0: System is not in Standby, STANDBY = 1: System is in Standby

26.

The state of the STANDBY pin only has influence in On mode.

27.

Bit 6 in Power Control Register (ADDR - 0x1B)

Table 23. STANDBY Delay - Initiated Response

STBYDLY[1:0](28)

Function

No Delay

One 32 k period (default)

Two 32 k periods

Three 32 k periods

Notes

28.

Bits [5:4] in Power Control Register (ADDR - 0x1B)

MMPF0100 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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