MMPF0100 datasheet(36/136 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Power Generation

Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate

of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic Voltage Scaling. For

each regulator, the output voltage options are the same for Normal and Standby modes.

When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode

selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its

output voltage programmed in its voltage register.

Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a PWRON turn-off event occurs, and any regulator

whose SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off

(Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any

regulator whose SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep

state to the ON state. Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up

sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch

mode settings.

Table 24 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the

set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.

Dynamic Voltage Scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the

processor.

1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B,

and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.

2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the

lowest state retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits

SWxSTBY[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a Standby event are governed by the

SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.

3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest

state retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits

SWxOFF[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the

SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.

Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators.

1110

Reserved

1111

Reserved

Table 31. DVS Control Logic for SW1A/B/C

STANDBY

Set Point Selected by

SW1x[5:0]

SW1xSTBY[5:0]

Table 32. DVS Control Logic for SW2, SW3A/B, and SW4

STANDBY

Set Point Selected by

SWx[6:0]

SWxSTBY[6:0]

Table 30. Regulator Mode Control

SWxMODE[3:0]

Normal Mode

Standby Mode

MMPF0100 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

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