MMPF0100 datasheet(86/136 Pages) FREESCALE

86 / 136 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Power Generation

For more detail information, Table 94 through Table 99 provide a description of all registers necessary to operate all six general

purpose LDO regulators.

Table 94. Register VGEN1CTL - ADDR 0x6C

Name

Bit #

R/W

Default

Description

VGEN1

3:0

R/W

0x80

Sets VGEN1 output voltage.

See Table 91 for all possible configurations.

VGEN1EN

–

0x00

Enables or Disables VGEN1 output

0 = OFF

1 = ON

VGEN1STBY

R/W

0x00

Set VGEN1 output state when in Standby. Refer

to Table 93.

VGEN1LPWR

R/W

0x00

Enable Low Power Mode for VGEN1. Refer to

Table 93.

UNUSED

–

0x00

UNUSED

Table 95. Register VGEN2CTL - ADDR 0x6D

Name

Bit #

R/W

Default

Description

VGEN2

3:0

R/W

0x80

Sets VGEN2 output voltage.

See Table 91 for all possible configurations.

VGEN2EN

–

0x00

Enables or Disables VGEN2 output

0 = OFF

1 = ON

VGEN2STBY

R/W

0x00

Set VGEN2 output state when in Standby. Refer

to Table 93.

VGEN2LPWR

R/W

0x00

Enable Low Power Mode for VGEN2. Refer to

Table 93.

UNUSED

–

0x00

UNUSED

Table 96. Register VGEN3CTL - ADDR 0x6E

Name

Bit #

R/W

Default

Description

VGEN3

3:0

R/W

0x80

Sets VGEN3 output voltage.

See Table 92 for all possible configurations.

VGEN3EN

–

0x00

Enables or Disables VGEN3 output

0 = OFF

1 = ON

VGEN3STBY

R/W

0x00

Set VGEN3 output state when in Standby. Refer

to Table 93.

VGEN3LPWR

R/W

0x00

Enable Low Power Mode for VGEN3. Refer to

Table 93.

UNUSED

–

0x00

UNUSED

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