MMPF0100 datasheet(37/136 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Power Generation

The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling

slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during

a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced,

controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode

operation.

The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control.

During the DVS period the over-current condition on the regulator should be masked.

Actual

Output Voltage

Example

Actual Output

Voltage

Possible

Output Voltage

Window

Internally

Controlled Steps

Output Voltage

with light Load

Initial

Set Point

Voltage

Change

Request

Internally

Controlled Steps

Output

Voltage

Requested

Set Point

Initiated by I2C Programming, Standby Control

Request for

Higher Voltage

Request for

Lower Voltage

Figure 9. Voltage Stepping with DVS

Regulator Phase Clock

The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 35. By default, each regulator is initialized at

90 ° out of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and

SW4 is set to 270 ° by default at power up.

Table 33. DVS Speed Selection for SW1A/B/C

SW1xDVSSPEED[1:0]

Function

25 mV step each 2.0

μs

01 (default)

25 mV step each 4.0

μs

25 mV step each 8.0

μs

25 mV step each 16

μs

Table 34. DVS Speed Selection for SW2, SW3A/B, and SW4

SWxDVSSPEED[1:0]

Function

SWx[6] = 0 or SWxSTBY[6] = 0

Function

SWx[6] = 1 or SWxSTBY[6] = 1

25 mV step each 2.0

μs

50 mV step each 4.0

μs

01 (default)

25 mV step each 4.0

μs

50 mV step each 8.0

μs

25 mV step each 8.0

μs

50 mV step each 16

μs

25 mV step each 16

μs

50 mV step each 32

μs

MMPF0100 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc

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