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STRH100N10 Datasheet(PDF) 5 Page - STMicroelectronics |
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STRH100N10 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 17 page ![]() STRH100N10 Electrical characteristics Doc ID 17486 Rev 6 5/17 2 Electrical characteristics (TC = 25 °C unless otherwise specified). Pre-irradiation Table 5. Pre-irradiation on/off states Symbol Parameter Test conditions Min. Typ. Max. Unit IDSS Zero gate voltage drain current (VGS = 0) 80% BVDss 10 µA IGSS Gate body leakage current (VDS = 0) VGS = 20 V VGS = -20 V -100 100 nA nA BVDSS (1) 1. This rating is guaranteed @ TJ ≥ 25 °C (see Figure 10: Normalized BVDSS vs temperature). Drain-to-source breakdown voltage VGS = 0, ID = 1 mA 100 V VGS(th) Gate threshold voltage VDS = VGS, ID = 1 mA 2 4.5 V RDS(on) Static drain-source on resistance VGS = 12 V; ID = 24 A 0.030 0.035 Ω Table 6. Pre-irradiation dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Coss (1) Crss Input capacitance Output capacitance Reverse transfer capacitance VGS = 0, VDS = 25 V, f=1 MHz 3940 543 190 4925 679 237 5910 814 284 pF pF pF Coss eq. (1) 1. This value is guaranteed over the full range of temperature. Equivalent output capacitance (2) 2. This value is defined as the ratio between the Qoss and the voltage value applied. VGS = 0, VDD = 80 V 480 pF Qg Qgs Qgd Total gate charge Gate-to-source charge Gate-to-drain (“Miller”) charge VDD = 50 V, ID = 48 A, VGS=12 V 108 21 36 135 27 45 162 33 54 nC nC nC RG (3) 3. Not tested, guaranteed by process. Gate input resistance f=1MHz gate DC bias=0 test signal level=20mV open drain 1.2 1.7 2 Ω LG Gate inductance 4.5 nH LS Source inductance 7.5 nH LD Drain inductance 7.5 nH |
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