RT9367C datasheet(16/18 Pages) RICHTEK

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RT9367C

DS9367C-01 March 2011

www.richtek.com

Figure 8. illustrates the dual LDOs' output voltage and

LED current setting information. The output voltage of LDO1

could be divided to 32-step levels between 1.75V (HEX

Code = 0) and 3.3V (HEX Code = 1F). And the output

voltage of LDO2 is separated to two regions, one is from

1.1V (HEX Code = 0) to 1.8V (HEX Code = 0E) and the

other is from 2.5V (HEX Code = 0F) to 3.3V (HEX Code =

1F). In addition, the LED current could be divided to 32-

step levels between 0.8mA (HEX Code = 0) and 25mA

(HEX Code = 1F).

Voltage (V)

Code

C4~C0

LDO1

LDO2

Code

C4~C0

LDO1

LDO2

Code

C4~C0

LDO1

LDO2

Code

C4~C0

LDO1

LDO2

00000

1.75

1.10

01000

2.15

1.50

10000

2.55

11000

2.95

00001

1.80

1.15

01001

2.20

1.55

10001

2.60

11001

3.00

00010

1.85

1.20

01010

2.25

1.60

10010

2.65

11010

3.05

00011

1.90

1.25

01011

2.30

1.65

10011

2.70

11011

3.10

00100

1.95

1.30

01100

2.35

1.70

10100

2.75

11100

3.15

00101

2.00

1.35

01101

2.40

1.75

10101

2.80

11101

3.20

00110

2.05

1.40

01110

2.45

1.80

10110

2.85

11110

3.25

00111

2.10

1.45

01111

2.50

10111

2.90

11111

3.30

Code

C4~C0

LED Current

(mA)

Code

C4~C0

LED Current

(mA)

Code

C4~C0

LED Current

(mA)

Code

C4~C0

LED Current

(mA)

00000

0.8

01000

7.0

10000

13.3

11000

19.5

00001

1.6

01001

7.8

10001

14.0

11001

20.3

00010

2.3

01010

8.6

10010

14.8

11010

21.1

00011

3.1

01011

9.4

10011

15.6

11011

21.8

00100

3.9

01100

10.1

10100

16.4

11100

22..6

00101

4.7

01101

10.9

10101

17.2

11101

23.4

00110

5.5

01110

11.7

10110

17.9

11110

24.2

00111

6.2

01111

12.5

10111

18.7

11111

25.0

Table 1. LDO Voltage Setting

Table 2. LDO Current Setting

Layout Consideration

The RT9367C is a high-frequency switched-capacitor

converter. Careful PCB layout is necessary. For best

performance, place all peripheral components as close to

the IC as possible. Place CIN1, CIN2, COUT, CLDO1, CLDO2,

CFLY1, and CFLY2 near to AVIN, PVIN, VOUT, LDO1, LDO2,

C1P, C1N, C2P, C2N, and GND pin respectively. A short

connection is highly recommended. The following

guidelines should be strictly followed when designing a

PCB layout for the RT9367C.

The exposed GND pad must be soldered to a large

ground plane for heat sinking and noise prevention. The

throughhole vias located at the exposed pad is

connected to ground plane of internal layer.

VIN traces should be wide enough to minimize

inductance and handle the high currents. The trace

running from battery to chip should be placed carefully

and shielded strictly.

Input and output capacitors must be placed close to the

part. The connection between pins and capacitor pads

should be copper traces without any through-hole via

connection.

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