AT91SAM datasheet(27/67 Pages) ATMEL

27 / 67 page

11100BS–ATARM–31-Jul-12

SAM4S Series [Preliminary]

Notes:

1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the

user application sets PB12 into PIO mode,

2. In the product Datasheet refer to: “Slow Clock Generator” of the “Supply Controller” section.

3. In the product Datasheet refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.

6.2.1

Serial Wire JTAG Debug Port (SWJ-DP) Pins

The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on

a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference

and reset state, refer to Table 3-1 on page 8.

At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging

probe. Please refer to the “Debug and Test” Section of the product datasheet.

SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins

when the debug port is not needed in the end application. Mode selection between SWJ-DP

mode (System IO mode) and general IO mode is performed through the AHB Matrix Special

Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing

and glitch filters is possible regardless of the mode.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left uncon-

nected for normal operations.

By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial

Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and

TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire

Debug Port is active, TDO/TRACESWO can be used for trace.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous

trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and

JTAG-DP switching, please refer to the “Debug and Test” Section.

Table 6-1.

System I/O Configuration Pin List.

SYSTEM_IO

bit number

Default function

after reset

Other function

Constraints for

normal start

Configuration

ERASE

PB12

Low Level at startup(1)

In Matrix User Interface Registers

(Refer to the System I/O

Configuration Register in the “Bus

Matrix” section of the datasheet.)

DDM

PB10

DDP

PB11

TCK/SWCLK

PB7

TMS/SWDIO

PB6

TDO/TRACESWO

PB5

TDI

PB4

PA7

XIN32

See footnote

(2) below

PA8

XOUT32

PB9

XIN

See footnote

(3) below

PB8

XOUT

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