MAX11046 datasheet(14/27 Pages) MAXIM

14 / 27 page

4-/6-/8-Channel, 16-/14-Bit,

Simultaneous-Sampling ADCs

Maxim Integrated

MAX11044/MAX11045/MAX11046/

MAX11054/MAX11055/MAX11056

Pin Description (continued)

MAX11054

(TQFP-EP)

MAX11055

(TQFP-EP)

MAX11056

(TQFP-EP)

NAME

FUNCTION

DB12

14-Bit Parallel Data Bus Digital Output Bit 12

DB11

14-Bit Parallel Data Bus Digital Output Bit 11

DB10

14-Bit Parallel Data Bus Digital Output Bit 10

DB9

14-Bit Parallel Data Bus Digital Output Bit 9

DB8

14-Bit Parallel Data Bus Digital Output Bit 8

DB7

14-Bit Parallel Data Bus Digital Output Bit 7

DB6

14-Bit Parallel Data Bus Digital Output Bit 6

8, 22, 59

DGND

Digital Ground

9, 21, 60

DVDD

Digital Supply. Bypass to DGND with a 0.1µF capacitor

at each DVDD input.

DB5

14-Bit Parallel Data Bus Digital Output Bit 5

DB4

14-Bit Parallel Data Bus Digital Output Bit 4

DB3

14-Bit Parallel Data Bus Digital Output Bit 3

DB2

14-Bit Parallel Data Bus Digital Output Bit 2

DB1/CR3

14-Bit Parallel Data Bus Digital Output Bit 1/

Configuration Register Input Bit 3

DB0/CR2

14-Bit Parallel Data Bus Digital Output Bit 0/

Configuration Register Input Bit 2

CR1

Configuration Register Input Bit 1

CR0

Configuration Register Input Bit 0

EOC

Active-Low End-of-Conversion Output. EOC goes low

when conversion is completed. EOC goes high when a

conversion is initiated.

CONVST

Convert Start Input. Rising edge of CONVST ends

sample and starts a conversion on the captured sample.

The ADC is in acquisition mode when CONVST is low

and CONVST mode = 0.

SHDN

Shutdown Input. If SHDN is held high, the entire device

will enter and stay in a low-current state. Contents of

the configuration register are not lost when in the

shutdown mode.

23, 28, 32, 38,

43, 49, 53, 58

23, 28, 32, 38,

43, 49, 53, 58

23, 28, 32, 38,

43, 49, 53, 58

AGNDS

Signal Ground. Connect all AGND and AGNDS inputs

together on PCB.

24, 29, 35, 46,

52, 57

24, 29, 35, 46,

52, 57

24, 29, 35, 46,

52, 57

AVDD

Analog Supply Input. Bypass AVDD to AGND with a

0.1µF capacitor at each AVDD input.

25, 30, 36, 45,

51, 56

25, 30, 36, 45,

51, 56

25, 30, 36, 45,

51, 56

AGND

Analog Ground. Connect all AGND inputs together.

26, 55

RDC_SENSE

Reference Buffer Sense Feedback. Connect to RDC plane.

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