MAX11046 datasheet(15/27 Pages) MAXIM

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4-/6-/8-Channel, 16-/14-Bit,

Simultaneous-Sampling ADCs

Maxim Integrated

MAX11044/MAX11045/MAX11046/

MAX11054/MAX11055/MAX11056

Detailed Description

The MAX11044/MAX11045/MAX11046 and MAX11054/

MAX11055/MAX11056 are fast, low-power ADCs that

combine 4, 6, or 8 independent ADC channels in a sin-

gle IC. Each channel includes simultaneously sampling

independent T/H circuitry that preserves relative phase

information between inputs making the MAX11044/

MAX11045/MAX11046 and MAX11054/MAX11055/

MAX11056 ideal for motor control and power monitor-

ing. The MAX11044/MAX11045/MAX11046 and

MAX11054/MAX11055/MAX11056 are available with

±5V input ranges that feature ±20mA overrange, fault-

tolerant inputs. The MAX11044/MAX11045/MAX11046

and MAX11054/MAX11055/MAX11056 operate with a

single 4.75V to 5.25V supply. A separate 2.7V to 5.25V

supply for digital circuitry makes the devices compatible

with low-voltage processors.

The MAX11044/MAX11045/MAX11046 and MAX11054/

MAX11055/MAX11056 perform conversions for all chan-

nels in parallel by activating independent ADCs. Results

are available through a high-speed, 20MHz, parallel

data bus after a conversion time of 3µs following the end

of a sample. The data bus is bidirectional and allows for

easy programming of the configuration register. The

MAX11044/MAX11045/MAX11046 and MAX11054/

MAX11055/MAX11056 feature a reference buffer, which

Pin Description (continued)

MAX11054

(TQFP-EP)

MAX11055

(TQFP-EP)

MAX11056

(TQFP-EP)

NAME

FUNCTION

27, 33, 40, 48,

RDC

Reference Buffer Decoupling. Connect all RDC outputs

together. Bypass to AGND with at least an 80µF total

capacitance. See the Layout, Grounding, and Bypassing

section.

CH0

Channel 0 Analog Input

CH1

Channel 1 Analog Input

CH2

Channel 2 Analog Input

CH3

Channel 3 Analog Input

REFIO

External Reference Input/Internal Reference Output.

Place a 0.1µF capacitor from REFIO to AGND.

—

CH4

Channel 4 Analog Input

—

CH5

Channel 5 Analog Input

—

CH6

Channel 6 Analog Input

—

CH7

Channel 7 Analog Input

Active-Low Write Input. Drive WR low to write to the

ADC. Configuration registers are loaded on the rising

edge of WR.

Active-Low Chip-Select Input. Drive CS low when

reading from or writing to the ADC.

Active-Low Read Input. Drive RD low to read from the

ADC. Each rising edge of RD advances the channel

output on the data bus.

DB13

14-Bit Parallel Data Bus Digital Output Bit 13

31, 34, 47, 50

31, 50

—

I.C.

Internally Connected. Connect to AGND.

———

Exposed Pad. Internally connected to AGND. Connect to

a large ground plane to maximize thermal performance.

Not intended as an electrical connection point.

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